OV - exec - Function qmcplusplus::SPOSet::evaluateDetRatios(qmcplusplus::VirtualParticleSet const&, qmcplusplus::Vector<double, std::allocator<double> >&, qmcplusplus::Vector<double, std::allocator<double> > const&, std::vector<double, std::allocator<double> >&)

	Function: qmcplusplus::SPOSet::evaluateDetRatios(qmcplusplus::VirtualParticleSet const&, qmcplusplus ...	Module: exec	Source: SPOSet.h:83-88 [...]	Coverage (incl. loops): 0.04% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 82 - 83

--------------------------------------------------------------------------------

82:   for (int i = 0; i < n; i++)

83:     res += a[i] * b[i];

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1046

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h: 83 - 88

--------------------------------------------------------------------------------

83:     for (int iat = 0; iat < VP.getTotalNum(); ++iat)

84:     {

85:       evaluate(VP, iat, psi);

86:       ratios[iat] = simd::dot(psi.data(), psiinv.data(), psi.size());

87:     }

88:   }

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 178 - 178

--------------------------------------------------------------------------------

178:   inline size_t size() const { return nLocal; }

0x25b380 CMPQ	$0,0x260(%RSI)

0x25b388 JE	25b546

0x25b38e PUSH	%RBP

0x25b38f MOV	%RSP,%RBP

0x25b392 PUSH	%R15

0x25b394 PUSH	%R14

0x25b396 PUSH	%R13

0x25b398 PUSH	%R12

0x25b39a PUSH	%RBX

0x25b39b PUSH	%RAX

0x25b39c MOV	%RDI,%R14

0x25b39f MOV	%RSI,%R15

0x25b3a2 MOV	%RDX,%R12

0x25b3a5 MOV	%RCX,-0x30(%RBP)

0x25b3a9 MOV	%R8,%R13

0x25b3ac XOR	%EBX,%EBX

0x25b3ae JMP	25b3cd

(840) 0x25b3b0 VXORPD	%XMM0,%XMM0,%XMM0

(840) 0x25b3b4 MOV	(%R13),%RAX

(840) 0x25b3b8 VMOVSD	%XMM0,(%RAX,%RBX,8)

(840) 0x25b3bd INC	%RBX

(840) 0x25b3c0 CMP	%RBX,0x260(%R15)

(840) 0x25b3c7 JBE	25b538

(840) 0x25b3cd MOV	(%R14),%RAX

(840) 0x25b3d0 MOV	%R14,%RDI

(840) 0x25b3d3 MOV	%R15,%RSI

(840) 0x25b3d6 MOV	%EBX,%EDX

(840) 0x25b3d8 MOV	%R12,%RCX

(840) 0x25b3db VZEROUPPER

(840) 0x25b3de CALLQ	0x10(%RAX)

(840) 0x25b3e1 MOV	0x8(%R12),%RDX

(840) 0x25b3e6 TEST	%EDX,%EDX

(840) 0x25b3e8 JLE	25b3b0

(840) 0x25b3ea MOV	-0x30(%RBP),%RCX

(840) 0x25b3ee MOV	0x18(%R12),%RAX

(840) 0x25b3f3 MOV	%EDX,%EDX

(840) 0x25b3f5 MOV	0x18(%RCX),%RCX

(840) 0x25b3f9 CMP	$0x4,%EDX

(840) 0x25b3fc JAE	25b410

(840) 0x25b3fe VXORPD	%XMM0,%XMM0,%XMM0

(840) 0x25b402 XOR	%ESI,%ESI

(840) 0x25b404 JMP	25b520

0x25b409 NOPL	(%RAX)

(840) 0x25b410 CMP	$0x20,%EDX

(840) 0x25b413 JAE	25b420

(840) 0x25b415 VXORPD	%XMM0,%XMM0,%XMM0

(840) 0x25b419 XOR	%ESI,%ESI

(840) 0x25b41b JMP	25b4c7

(840) 0x25b420 MOV	%EDX,%EDI

(840) 0x25b422 MOV	%EDX,%ESI

(840) 0x25b424 AND	$0x1f,%EDI

(840) 0x25b427 AND	$-0x20,%ESI

(840) 0x25b42a VXORPD	%XMM0,%XMM0,%XMM0

(840) 0x25b42e VXORPD	%XMM1,%XMM1,%XMM1

(840) 0x25b432 VXORPD	%XMM2,%XMM2,%XMM2

(840) 0x25b436 VXORPD	%XMM3,%XMM3,%XMM3

(840) 0x25b43a XOR	%R8D,%R8D

(840) 0x25b43d NOPL	(%RAX)

  (841) 0x25b440 VMOVUPD	(%RCX,%R8,8),%ZMM4

  (841) 0x25b447 VMOVUPD	0x40(%RCX,%R8,8),%ZMM5

  (841) 0x25b44f VMOVUPD	0x80(%RCX,%R8,8),%ZMM6

  (841) 0x25b457 VMOVUPD	0xc0(%RCX,%R8,8),%ZMM7

  (841) 0x25b45f VFMADD231PD	(%RAX,%R8,8),%ZMM4,%ZMM0

  (841) 0x25b466 VFMADD231PD	0x40(%RAX,%R8,8),%ZMM5,%ZMM1

  (841) 0x25b46e VFMADD231PD	0x80(%RAX,%R8,8),%ZMM6,%ZMM2

  (841) 0x25b476 VFMADD231PD	0xc0(%RAX,%R8,8),%ZMM7,%ZMM3

  (841) 0x25b47e ADD	$0x20,%R8

  (841) 0x25b482 CMP	%R8,%RSI

  (841) 0x25b485 JNE	25b440

(840) 0x25b487 VADDPD	%ZMM0,%ZMM1,%ZMM0

(840) 0x25b48d VADDPD	%ZMM2,%ZMM3,%ZMM2

(840) 0x25b493 VADDPD	%ZMM0,%ZMM2,%ZMM0

(840) 0x25b499 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

(840) 0x25b4a0 VADDPD	%ZMM1,%ZMM0,%ZMM0

(840) 0x25b4a6 VEXTRACTF128	$0x1,%YMM0,%XMM1

(840) 0x25b4ac VADDPD	%XMM1,%XMM0,%XMM0

(840) 0x25b4b0 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

(840) 0x25b4b5 VADDSD	%XMM1,%XMM0,%XMM0

(840) 0x25b4b9 TEST	%RDI,%RDI

(840) 0x25b4bc JE	25b3b4

(840) 0x25b4c2 CMP	$0x4,%EDI

(840) 0x25b4c5 JB	25b520

(840) 0x25b4c7 MOV	%EDX,%EDI

(840) 0x25b4c9 MOV	%RSI,%R8

(840) 0x25b4cc MOV	%EDX,%ESI

(840) 0x25b4ce AND	$0x3,%EDI

(840) 0x25b4d1 AND	$-0x4,%ESI

(840) 0x25b4d4 VMOVQ	%XMM0,%XMM0

(840) 0x25b4d8 NOPL	(%RAX,%RAX,1)

  (843) 0x25b4e0 VMOVUPD	(%RCX,%R8,8),%YMM1

  (843) 0x25b4e6 VFMADD231PD	(%RAX,%R8,8),%YMM1,%YMM0

  (843) 0x25b4ec ADD	$0x4,%R8

  (843) 0x25b4f0 CMP	%R8,%RSI

  (843) 0x25b4f3 JNE	25b4e0

(840) 0x25b4f5 VEXTRACTF128	$0x1,%YMM0,%XMM1

(840) 0x25b4fb VADDPD	%XMM1,%XMM0,%XMM0

(840) 0x25b4ff VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

(840) 0x25b504 VADDSD	%XMM1,%XMM0,%XMM0

(840) 0x25b508 TEST	%RDI,%RDI

(840) 0x25b50b JE	25b3b4

(840) 0x25b511 NOPW	%CS:(%RAX,%RAX,1)

  (842) 0x25b520 VMOVSD	(%RCX,%RSI,8),%XMM1

  (842) 0x25b525 VFMADD231SD	(%RAX,%RSI,8),%XMM1,%XMM0

  (842) 0x25b52b INC	%RSI

  (842) 0x25b52e CMP	%RSI,%RDX

  (842) 0x25b531 JNE	25b520

(840) 0x25b533 JMP	25b3b4

0x25b538 ADD	$0x8,%RSP

0x25b53c POP	%RBX

0x25b53d POP	%R12

0x25b53f POP	%R13

0x25b541 POP	%R14

0x25b543 POP	%R15

0x25b545 POP	%RBP

0x25b546 VZEROUPPER

0x25b549 RET

0x25b54a INT	$0x3

0x25b54b INT	$0x3

0x25b54c INT	$0x3

0x25b54d INT	$0x3

0x25b54e INT	$0x3

0x25b54f INT	$0x3

Coverage (%)	Name	Source Location	Module
►92.82+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:217	exec
○	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:919	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.omp_outlined.64	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.62+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:217	exec
○	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:919	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.omp_outlined.64	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:411	exec
○	__libc_start_call_main		libc.so.6
►2.68+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:919	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.omp_outlined.64	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	SPOSet.h:83-88
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:83-88
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 3.25 to 0.23 cycles (13.89x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	33
nb uops	26
loop length	79
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	1.00	1.00	1.00	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	0.67	0.67	0.67	1.00	1.00	1.00	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.25
Dispatch	1.00
Overall L1	3.25

Vectorization ratios

all	12%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.25 cycles. At this rate:

0% of peak load performance is reached (2.46 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.46 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.25 to 1.00 cycles (3.25x speedup).

ASM code

In the binary file, the address of the function is: 25b380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
CMPQ $0,0x260(%RSI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 25b546 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x1c6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RSI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 25b3cd <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x4d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	SPOSet.h:83-88
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:83-88
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	33
nb uops	26
loop length	79
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	1.00	1.00	1.00	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	0.67	0.67	0.67	1.00	1.00	1.00	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.25
Dispatch	1.00
Overall L1	3.25

Vectorization ratios

all	12%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.25 cycles. At this rate:

0% of peak load performance is reached (2.46 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.46 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 25b380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
CMPQ $0,0x260(%RSI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 25b546 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x1c6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RSI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 25b3cd <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x4d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A

Name	Coverage (%)	Time (s)
▼qmcplusplus::SPOSet::evaluateDetRatios(qmcplusplus::VirtualParticleSet const&, qmcplusplus::Vector >&, qmcplusplus::Vector > const&, std::vector >&)–	0.04	0.07
▼Loop 840 - inner_product.hpp:82-83 - exec–	0.00	0.01
○Loop 841 - inner_product.hpp:82-83 - exec	0.04	0.06
○Loop 843 - inner_product.hpp:82-83 - exec	0.00	0.00
○Loop 842 - inner_product.hpp:82-83 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code