OV - exec - Function miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector<double, std::allocator<double> >&)

	Function: miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios( ...	Module: exec	Source: TwoBodyJastrowRef.h:106-132 [...]	Coverage (incl. loops): 1.08% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 313 - 316

--------------------------------------------------------------------------------

313:   inline int first(int igroup) const { return (*group_offsets_)[igroup]; }

314:

315:   ///return the last index of a group i

316:   inline int last(int igroup) const { return (*group_offsets_)[igroup + 1]; }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/optional: 433 - 952

--------------------------------------------------------------------------------

433:       { return static_cast<const _Dp*>(this)->_M_payload._M_engaged; }

[...]

950: 	if (this->_M_is_engaged())

951: 	  return this->_M_get();

952: 	__throw_bad_optional_access();

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 106 - 132

--------------------------------------------------------------------------------

106:   {

107:     for (int k = 0; k < ratios.size(); ++k)

108:       ratios[k] = std::exp(Uat[VP.refPtcl] - computeU(VP.getRefPS(), VP.refPtcl, VP.getDistTableAB(myTableID).getDistRow(k).data()));

109:   }

[...]

126:     const int igt = P.GroupID[iat] * NumGroups;

127:     for (int jg = 0; jg < NumGroups; ++jg)

128:     {

129:       const FuncType& f2(*F[igt + jg]);

130:       int iStart = P.first(jg);

131:       int iEnd   = P.last(jg);

132:       curUat += f2.evaluateV(iat, iStart, iEnd, dist, DistCompressed.data());

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 236 - 260

--------------------------------------------------------------------------------

236:   for (int jat = 0; jat < iLimit; jat++)

237:   {

238:     real_type r = distArray[jat];

239:     // pick the distances smaller than the cutoff and avoid the reference atom

240:     if (r < cutoff_radius && iStart + jat != iat)

241:       distArrayCompressed[iCount++] = distArray[jat];

242:   }

243:

244:   real_type d = 0.0;

245:   //#pragma omp simd reduction(+:d)

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 919 - 1064

--------------------------------------------------------------------------------

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1046: 	return *(this->_M_impl._M_start + __n);

[...]

1064: 	return *(this->_M_impl._M_start + __n);

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/refwrap.h: 338 - 338

--------------------------------------------------------------------------------

338:       { return *_M_data; }

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 229 - 229

--------------------------------------------------------------------------------

229:     return X[i];

0x23f9d0 PUSH	%RBP

0x23f9d1 MOV	%RSP,%RBP

0x23f9d4 PUSH	%R15

0x23f9d6 PUSH	%R14

0x23f9d8 PUSH	%R13

0x23f9da PUSH	%R12

0x23f9dc PUSH	%RBX

0x23f9dd AND	$-0x40,%RSP

0x23f9e1 SUB	$0x200,%RSP

0x23f9e8 MOV	0x8(%RDX),%RAX

0x23f9ec CMP	%RAX,(%RDX)

0x23f9ef JE	24030c

0x23f9f5 XOR	%R14D,%R14D

0x23f9f8 XOR	%EAX,%EAX

0x23f9fa MOV	%RDI,0x20(%RSP)

0x23f9ff MOV	%RSI,0x28(%RSP)

0x23fa04 MOV	%RDX,0x40(%RSP)

0x23fa09 MOV	%RAX,0x30(%RSP)

0x23fa0e JMP	23fa5b

(324) 0x23fa10 VXORPD	%XMM14,%XMM14,%XMM14

(324) 0x23fa15 VMOVSD	0x50(%RSP),%XMM0

(324) 0x23fa1b VSUBSD	%XMM14,%XMM0,%XMM0

(324) 0x23fa20 VZEROUPPER

(324) 0x23fa23 CALL	2f6fa0 <@plt_start@+0x360>

(324) 0x23fa28 MOV	0x40(%RSP),%RAX

(324) 0x23fa2d MOV	0x30(%RSP),%RDX

(324) 0x23fa32 MOV	(%RAX),%RCX

(324) 0x23fa35 MOV	0x40(%RSP),%RAX

(324) 0x23fa3a VMOVSD	%XMM0,(%RCX,%RDX,8)

(324) 0x23fa3f INC	%RDX

(324) 0x23fa42 MOV	0x8(%RAX),%RAX

(324) 0x23fa46 MOV	%RDX,0x30(%RSP)

(324) 0x23fa4b SUB	%RCX,%RAX

(324) 0x23fa4e SAR	$0x3,%RAX

(324) 0x23fa52 CMP	%RDX,%RAX

(324) 0x23fa55 JBE	24030c

(324) 0x23fa5b MOV	0x28(%RSP),%RAX

(324) 0x23fa60 CMPB	$0,0x298(%RAX)

(324) 0x23fa67 JE	24031b

(324) 0x23fa6d MOV	0x28(%RSP),%RAX

(324) 0x23fa72 MOV	0x20(%RSP),%RCX

(324) 0x23fa77 MOV	0x28(%RSP),%RDX

(324) 0x23fa7c MOV	0x28(%RSP),%RDI

(324) 0x23fa81 MOVSXD	0x2a0(%RAX),%R15

(324) 0x23fa88 MOV	0xd8(%RCX),%RAX

(324) 0x23fa8f MOV	0x20(%RSP),%RCX

(324) 0x23fa94 MOV	0x290(%RDX),%RBX

(324) 0x23fa9b VMOVSD	(%RAX,%R15,8),%XMM0

(324) 0x23faa1 MOV	0x248(%RCX),%ESI

(324) 0x23faa7 VMOVSD	%XMM0,0x50(%RSP)

(324) 0x23faad CALL	27d7e0 <_ZNK11qmcplusplus11ParticleSet14getDistTableABEi>

(324) 0x23fab2 MOV	0x20(%RSP),%RCX

(324) 0x23fab7 MOV	0xa0(%RCX),%R9

(324) 0x23fabe TEST	%R9,%R9

(324) 0x23fac1 JE	23fa10

(324) 0x23fac7 MOV	0x30(%RSP),%RCX

(324) 0x23facc MOV	0x48(%RAX),%RAX

(324) 0x23fad0 VPBROADCASTQ	%R15,%ZMM15

(324) 0x23fad6 VXORPD	%XMM14,%XMM14,%XMM14

(324) 0x23fadb MOV	%R15,%R8

(324) 0x23fade XOR	%R12D,%R12D

(324) 0x23fae1 MOV	%R8,0x68(%RSP)

(324) 0x23fae6 MOV	%R9,0x60(%RSP)

(324) 0x23faeb VMOVDQA64	%ZMM15,0x180(%RSP)

(324) 0x23faf3 LEA	(%RCX,%RCX,4),%RDX

(324) 0x23faf7 MOV	0x20(%RSP),%RCX

(324) 0x23fafc MOV	0x18(%RAX,%RDX,8),%R10

(324) 0x23fb01 MOV	0x18(%RBX),%RAX

(324) 0x23fb05 MOV	0x20(%RSP),%RDX

(324) 0x23fb0a MOV	0x1d0(%RCX),%RSI

(324) 0x23fb11 MOV	0x268(%RBX),%RCX

(324) 0x23fb18 MOV	(%RAX,%R15,4),%EAX

(324) 0x23fb1c MOV	%R10,0x58(%RSP)

(324) 0x23fb21 IMUL	%R9D,%EAX

(324) 0x23fb25 CLTQ

(324) 0x23fb27 MOV	%RAX,0x80(%RSP)

(324) 0x23fb2f MOV	0x200(%RDX),%RAX

(324) 0x23fb36 MOV	%RAX,0x78(%RSP)

(324) 0x23fb3b MOV	0x18(%RCX),%RAX

(324) 0x23fb3f MOV	%RAX,0x88(%RSP)

(324) 0x23fb47 MOV	(%RAX),%EAX

(324) 0x23fb49 MOV	%EAX,%R15D

(324) 0x23fb4c JMP	23fb60

0x23fb4e XCHG	%AX,%AX

  (325) 0x23fb50 VADDSD	%XMM0,%XMM14,%XMM14

  (325) 0x23fb54 INC	%R12

  (325) 0x23fb57 CMP	%R9,%R12

  (325) 0x23fb5a JE	23fa15

  (325) 0x23fb60 MOV	0x88(%RSP),%RAX

  (325) 0x23fb68 MOV	%R15D,%EDI

  (325) 0x23fb6b VXORPD	%XMM0,%XMM0,%XMM0

  (325) 0x23fb6f MOV	0x4(%RAX,%R12,4),%R15D

  (325) 0x23fb74 MOV	%R15D,%EDX

  (325) 0x23fb77 SUB	%EDI,%EDX

  (325) 0x23fb79 JLE	23fb50

  (325) 0x23fb7b MOV	0x80(%RSP),%RAX

  (325) 0x23fb83 MOV	0x78(%RSP),%RCX

  (325) 0x23fb88 MOVSXD	%EDI,%RDI

  (325) 0x23fb8b MOV	%R12,0x48(%RSP)

  (325) 0x23fb90 MOV	%EDX,%EBX

  (325) 0x23fb92 LEA	(%R10,%RDI,8),%R11

  (325) 0x23fb96 ADD	%R12,%RAX

  (325) 0x23fb99 MOV	(%RCX,%RAX,8),%RAX

  (325) 0x23fb9d VMOVSD	0x8(%RAX),%XMM0

  (325) 0x23fba2 CMP	$0x8,%EDX

  (325) 0x23fba5 JAE	23fbc0

  (325) 0x23fba7 XOR	%R12D,%R12D

  (325) 0x23fbaa XOR	%EDX,%EDX

  (325) 0x23fbac JMP	23fcd0

0x23fbb1 NOPW	%CS:(%RAX,%RAX,1)

  (325) 0x23fbc0 VMOVDQA64	-0x36eca(%RIP),%ZMM3

  (325) 0x23fbca VBROADCASTSD	%XMM0,%ZMM1

  (325) 0x23fbd0 MOV	%EBX,%R12D

  (325) 0x23fbd3 AND	$-0x8,%R12D

  (325) 0x23fbd7 VPBROADCASTQ	%RDI,%ZMM2

  (325) 0x23fbdd MOV	%R15D,%ECX

  (325) 0x23fbe0 XOR	%R13D,%R13D

  (325) 0x23fbe3 XOR	%EDX,%EDX

  (325) 0x23fbe5 NOPW	%CS:(%RAX,%RAX,1)

    (326) 0x23fbf0 VMOVUPD	(%R11,%R13,8),%ZMM4

    (326) 0x23fbf7 VPADDQ	%ZMM2,%ZMM3,%ZMM5

    (326) 0x23fbfd VPADDQ	-0x3bb0f(%RIP){1to8},%ZMM3,%ZMM3

    (326) 0x23fc07 MOVSXD	%EDX,%RDX

    (326) 0x23fc0a VPCMPNEQQ	%ZMM15,%ZMM5,%K1

    (326) 0x23fc11 VCMPPD	$0x1,%ZMM1,%ZMM4,%K1{%K1}

    (326) 0x23fc18 KMOVB	%K1,%R15D

    (326) 0x23fc1c VCOMPRESSPD	%ZMM4,(%RSI,%RDX,8){%K1}

    (326) 0x23fc23 POPCNT	%R15D,%R15D

    (326) 0x23fc28 KORTESTB	%K1,%K1

    (326) 0x23fc2c CMOVE	%R14D,%R15D

    (326) 0x23fc30 ADD	$0x8,%R13

    (326) 0x23fc34 ADD	%R15D,%EDX

    (326) 0x23fc37 CMP	%R13,%R12

    (326) 0x23fc3a JNE	23fbf0

  (325) 0x23fc3c MOV	%ECX,%R15D

  (325) 0x23fc3f CMP	%RBX,%R12

  (325) 0x23fc42 JNE	23fcd0

  (325) 0x23fc48 MOV	0x48(%RSP),%R12

  (325) 0x23fc4d VXORPD	%XMM0,%XMM0,%XMM0

  (325) 0x23fc51 TEST	%EDX,%EDX

  (325) 0x23fc53 JLE	23fb50

  (325) 0x23fc59 VMOVSD	0x238(%RAX),%XMM16

  (325) 0x23fc60 VMOVUPD	0x18(%RAX),%XMM19

  (325) 0x23fc6a VMOVSD	0x28(%RAX),%XMM20

  (325) 0x23fc71 VMOVSD	0x30(%RAX),%XMM21

  (325) 0x23fc78 VMOVSD	0x38(%RAX),%XMM4

  (325) 0x23fc7d VMOVSD	0x40(%RAX),%XMM5

  (325) 0x23fc82 VMOVSD	0x48(%RAX),%XMM2

  (325) 0x23fc87 VMOVSD	0x50(%RAX),%XMM8

  (325) 0x23fc8c VMOVSD	0x58(%RAX),%XMM7

  (325) 0x23fc91 VMOVSD	0x60(%RAX),%XMM9

  (325) 0x23fc96 VMOVSD	0x68(%RAX),%XMM10

  (325) 0x23fc9b VMOVSD	0x70(%RAX),%XMM11

  (325) 0x23fca0 VMOVUPD	0x78(%RAX),%XMM6

  (325) 0x23fca5 VMOVSD	0x88(%RAX),%XMM17

  (325) 0x23fcac VMOVSD	0x90(%RAX),%XMM18

  (325) 0x23fcb3 MOV	0x218(%RAX),%R11

  (325) 0x23fcba MOV	%EDX,%EAX

  (325) 0x23fcbc CMP	$0x8,%EDX

  (325) 0x23fcbf JAE	23fd09

  (325) 0x23fcc1 XOR	%EBX,%EBX

  (325) 0x23fcc3 JMP	240241

0x23fcc8 NOPL	(%RAX,%RAX,1)

  (325) 0x23fcd0 MOV	%R8,%R13

  (325) 0x23fcd3 SUB	%RDI,%R13

  (325) 0x23fcd6 JMP	23fcec

0x23fcd8 NOPL	(%RAX,%RAX,1)

    (329) 0x23fce0 INC	%R12

    (329) 0x23fce3 CMP	%R12,%RBX

    (329) 0x23fce6 JE	23fc48

    (329) 0x23fcec CMP	%R12,%R13

    (329) 0x23fcef JE	23fce0

    (329) 0x23fcf1 VMOVSD	(%R11,%R12,8),%XMM1

    (329) 0x23fcf7 VUCOMISD	%XMM0,%XMM1

    (329) 0x23fcfb JAE	23fce0

    (329) 0x23fcfd MOVSXD	%EDX,%RCX

    (329) 0x23fd00 INC	%EDX

    (329) 0x23fd02 VMOVSD	%XMM1,(%RSI,%RCX,8)

    (329) 0x23fd07 JMP	23fce0

  (325) 0x23fd09 MOV	%EAX,%R12D

  (325) 0x23fd0c VMOVAPD	%XMM17,%XMM0

  (325) 0x23fd12 VMOVAPD	%XMM18,%XMM1

  (325) 0x23fd18 SHR	$0x3,%R12D

  (325) 0x23fd1c VMOVAPD	%XMM21,0x130(%RSP)

  (325) 0x23fd24 VBROADCASTSD	%XMM16,%YMM17

  (325) 0x23fd2a VBROADCASTSD	%XMM19,%YMM18

  (325) 0x23fd30 VMOVAPD	%YMM19,0x160(%RSP)

  (325) 0x23fd38 VPERMPD	$0x55,%YMM19,%YMM19

  (325) 0x23fd3f VBROADCASTSD	%XMM20,%YMM3

  (325) 0x23fd45 VBROADCASTSD	%XMM21,%YMM21

  (325) 0x23fd4b VBROADCASTSD	%XMM4,%YMM22

  (325) 0x23fd51 VBROADCASTSD	%XMM5,%YMM23

  (325) 0x23fd57 VBROADCASTSD	%XMM2,%YMM24

  (325) 0x23fd5d VBROADCASTSD	%XMM8,%YMM25

  (325) 0x23fd63 VBROADCASTSD	%XMM7,%YMM26

  (325) 0x23fd69 VMOVAPD	%XMM9,0xb0(%RSP)

  (325) 0x23fd72 VBROADCASTSD	%XMM9,%YMM27

  (325) 0x23fd78 VMOVAPD	%XMM10,0xa0(%RSP)

  (325) 0x23fd81 VBROADCASTSD	%XMM10,%YMM28

  (325) 0x23fd87 VBROADCASTSD	%XMM11,%YMM29

  (325) 0x23fd8d VBROADCASTSD	%XMM6,%YMM30

  (325) 0x23fd93 VPERMPD	$0x55,%YMM6,%YMM31

  (325) 0x23fd9a VBROADCASTSD	%XMM0,%YMM9

  (325) 0x23fd9f VBROADCASTSD	%XMM1,%YMM10

  (325) 0x23fda4 MOV	%EAX,%EBX

  (325) 0x23fda6 VMOVAPD	%XMM5,0xf0(%RSP)

  (325) 0x23fdaf VMOVAPD	%XMM2,0xd0(%RSP)

  (325) 0x23fdb8 AND	$-0x8,%EBX

  (325) 0x23fdbb VXORPD	%XMM2,%XMM2,%XMM2

  (325) 0x23fdbf VXORPD	%XMM5,%XMM5,%XMM5

  (325) 0x23fdc3 MOV	%R15D,0x3c(%RSP)

  (325) 0x23fdc8 VMOVSD	%XMM14,0x70(%RSP)

  (325) 0x23fdce VMOVAPD	%XMM16,0x150(%RSP)

  (325) 0x23fdd6 VMOVAPD	%XMM20,0x140(%RSP)

  (325) 0x23fdde VMOVAPD	%XMM4,0x100(%RSP)

  (325) 0x23fde7 VMOVAPD	%XMM8,0xc0(%RSP)

  (325) 0x23fdf0 VMOVAPD	%XMM7,0xe0(%RSP)

  (325) 0x23fdf9 VMOVAPD	%XMM11,0x90(%RSP)

  (325) 0x23fe02 VMOVAPD	%XMM0,0x120(%RSP)

  (325) 0x23fe0b VMOVAPD	%XMM1,0x110(%RSP)

  (325) 0x23fe14 XOR	%EDX,%EDX

  (325) 0x23fe16 SAL	$0x6,%R12

  (325) 0x23fe1a NOPW	(%RAX,%RAX,1)

    (327) 0x23fe20 VMULPD	(%RSI,%RDX,1),%YMM17,%YMM11

    (327) 0x23fe27 VMULPD	0x20(%RSI,%RDX,1),%YMM17,%YMM13

    (327) 0x23fe2f VMOVAPD	%YMM3,%YMM20

    (327) 0x23fe35 ADD	$0x40,%RDX

    (327) 0x23fe39 VCVTTPD2DQ	%YMM11,%XMM1

    (327) 0x23fe3e VCVTTPD2DQ	%YMM13,%XMM0

    (327) 0x23fe43 VROUNDPD	$0xb,%YMM11,%YMM12

    (327) 0x23fe49 VROUNDPD	$0xb,%YMM13,%YMM14

    (327) 0x23fe4f VPMOVSXDQ	%XMM1,%YMM4

    (327) 0x23fe54 VPMOVSXDQ	%XMM0,%YMM7

    (327) 0x23fe59 VSUBPD	%YMM12,%YMM11,%YMM12

    (327) 0x23fe5e VSUBPD	%YMM14,%YMM13,%YMM11

    (327) 0x23fe63 VPEXTRQ	$0x1,%XMM4,%RDI

    (327) 0x23fe69 VMOVQ	%XMM4,%R15

    (327) 0x23fe6e VEXTRACTI128	$0x1,%YMM4,%XMM4

    (327) 0x23fe74 VMOVQ	%XMM7,%RCX

    (327) 0x23fe79 VPEXTRQ	$0x1,%XMM7,%R14

    (327) 0x23fe7f VMOVQ	%XMM4,%R13

    (327) 0x23fe84 VPEXTRQ	$0x1,%XMM4,%R8

    (327) 0x23fe8a VEXTRACTI128	$0x1,%YMM7,%XMM4

    (327) 0x23fe90 VMOVSD	(%R11,%R15,8),%XMM7

    (327) 0x23fe96 VMOVSD	(%R11,%RCX,8),%XMM8

    (327) 0x23fe9c VMULPD	%YMM12,%YMM12,%YMM16

    (327) 0x23fea2 VFMADD213PD	%YMM21,%YMM11,%YMM20

    (327) 0x23fea8 VMULPD	%YMM11,%YMM11,%YMM15

    (327) 0x23fead VMOVQ	%XMM4,%R9

    (327) 0x23feb2 VPEXTRQ	$0x1,%XMM4,%R10

    (327) 0x23feb8 VMOVSD	(%R11,%R13,8),%XMM4

    (327) 0x23febe VMOVHPD	(%R11,%RDI,8),%XMM7,%XMM7

    (327) 0x23fec4 VMOVHPD	(%R11,%R14,8),%XMM8,%XMM8

    (327) 0x23feca VMOVHPD	(%R11,%R8,8),%XMM4,%XMM4

    (327) 0x23fed0 VMULPD	%YMM12,%YMM16,%YMM14

    (327) 0x23fed6 VMULPD	%YMM11,%YMM15,%YMM13

    (327) 0x23fedb VFMADD231PD	%YMM19,%YMM15,%YMM20

    (327) 0x23fee1 VFMADD231PD	%YMM18,%YMM13,%YMM20

    (327) 0x23fee7 VINSERTF128	$0x1,%XMM4,%YMM7,%YMM4

    (327) 0x23feed VMOVSD	(%R11,%R9,8),%XMM7

    (327) 0x23fef3 VMOVHPD	(%R11,%R10,8),%XMM7,%XMM7

    (327) 0x23fef9 VINSERTF128	$0x1,%XMM7,%YMM8,%YMM7

    (327) 0x23feff VMOVAPD	%YMM3,%YMM8

    (327) 0x23ff03 VFMADD213PD	%YMM21,%YMM12,%YMM8

    (327) 0x23ff09 VFMADD213PD	%YMM5,%YMM7,%YMM20

    (327) 0x23ff0f VMOVAPD	%YMM24,%YMM7

    (327) 0x23ff15 VFMADD213PD	%YMM25,%YMM11,%YMM7

    (327) 0x23ff1b VFMADD231PD	%YMM19,%YMM16,%YMM8

    (327) 0x23ff21 VFMADD231PD	%YMM23,%YMM15,%YMM7

    (327) 0x23ff27 VFMADD231PD	%YMM18,%YMM14,%YMM8

    (327) 0x23ff2d VFMADD231PD	%YMM22,%YMM13,%YMM7

    (327) 0x23ff33 VFMADD213PD	%YMM2,%YMM4,%YMM8

    (327) 0x23ff38 VPCMPEQD	%XMM4,%XMM4,%XMM4

    (327) 0x23ff3c VPSUBD	%XMM4,%XMM1,%XMM2

    (327) 0x23ff40 VPSUBD	%XMM4,%XMM0,%XMM4

    (327) 0x23ff44 VPMOVSXDQ	%XMM2,%YMM2

    (327) 0x23ff49 VPMOVSXDQ	%XMM4,%YMM4

    (327) 0x23ff4e VMOVQ	%XMM2,%RCX

    (327) 0x23ff53 VPEXTRQ	$0x1,%XMM2,%RDI

    (327) 0x23ff59 VEXTRACTI128	$0x1,%YMM2,%XMM2

    (327) 0x23ff5f VMOVQ	%XMM4,%R10

    (327) 0x23ff64 VPEXTRQ	$0x1,%XMM4,%R14

    (327) 0x23ff6a VPEXTRQ	$0x1,%XMM2,%R8

    (327) 0x23ff70 VMOVQ	%XMM2,%R9

    (327) 0x23ff75 VEXTRACTI128	$0x1,%YMM4,%XMM2

    (327) 0x23ff7b VMOVSD	(%R11,%RCX,8),%XMM4

    (327) 0x23ff81 VMOVSD	(%R11,%R10,8),%XMM5

    (327) 0x23ff87 VMOVQ	%XMM2,%R15

    (327) 0x23ff8c VPEXTRQ	$0x1,%XMM2,%R13

    (327) 0x23ff92 VMOVSD	(%R11,%R9,8),%XMM2

    (327) 0x23ff98 VMOVHPD	(%R11,%RDI,8),%XMM4,%XMM4

    (327) 0x23ff9e VMOVHPD	(%R11,%R14,8),%XMM5,%XMM5

    (327) 0x23ffa4 VMOVHPD	(%R11,%R8,8),%XMM2,%XMM2

    (327) 0x23ffaa VINSERTF128	$0x1,%XMM2,%YMM4,%YMM2

    (327) 0x23ffb0 VMOVSD	(%R11,%R15,8),%XMM4

    (327) 0x23ffb6 VMOVHPD	(%R11,%R13,8),%XMM4,%XMM4

    (327) 0x23ffbc VINSERTF128	$0x1,%XMM4,%YMM5,%YMM4

    (327) 0x23ffc2 VMOVAPD	%YMM24,%YMM5

    (327) 0x23ffc8 VFMADD213PD	%YMM25,%YMM12,%YMM5

    (327) 0x23ffce VFMADD213PD	%YMM20,%YMM4,%YMM7

    (327) 0x23ffd4 VMOVAPD	%YMM28,%YMM20

    (327) 0x23ffda VFMADD213PD	%YMM29,%YMM11,%YMM20

    (327) 0x23ffe0 VFMADD213PD	%YMM10,%YMM9,%YMM11

    (327) 0x23ffe5 VFMADD231PD	%YMM23,%YMM16,%YMM5

    (327) 0x23ffeb VFMADD231PD	%YMM27,%YMM15,%YMM20

    (327) 0x23fff1 VFMADD231PD	%YMM15,%YMM31,%YMM11

    (327) 0x23fff7 VFMADD231PD	%YMM22,%YMM14,%YMM5

    (327) 0x23fffd VFMADD231PD	%YMM26,%YMM13,%YMM20

    (327) 0x240003 VFMADD231PD	%YMM13,%YMM30,%YMM11

    (327) 0x240009 VFMADD213PD	%YMM8,%YMM2,%YMM5

    (327) 0x24000e VPBROADCASTD	-0x3bf47(%RIP),%XMM2

    (327) 0x240017 VPADDD	%XMM2,%XMM1,%XMM4

    (327) 0x24001b VPADDD	%XMM2,%XMM0,%XMM2

    (327) 0x24001f VPMOVSXDQ	%XMM4,%YMM4

    (327) 0x240024 VPMOVSXDQ	%XMM2,%YMM2

    (327) 0x240029 VMOVQ	%XMM4,%RCX

    (327) 0x24002e VPEXTRQ	$0x1,%XMM4,%RDI

    (327) 0x240034 VEXTRACTI128	$0x1,%YMM4,%XMM4

    (327) 0x24003a VMOVQ	%XMM2,%R14

    (327) 0x24003f VPEXTRQ	$0x1,%XMM2,%R10

    (327) 0x240045 VEXTRACTI128	$0x1,%YMM2,%XMM2

    (327) 0x24004b VMOVQ	%XMM4,%R8

    (327) 0x240050 VPEXTRQ	$0x1,%XMM4,%R9

    (327) 0x240056 VMOVSD	(%R11,%RCX,8),%XMM4

    (327) 0x24005c VMOVQ	%XMM2,%R15

    (327) 0x240061 VPEXTRQ	$0x1,%XMM2,%R13

    (327) 0x240067 VMOVSD	(%R11,%R14,8),%XMM8

    (327) 0x24006d VMOVSD	(%R11,%R8,8),%XMM2

    (327) 0x240073 VMOVHPD	(%R11,%RDI,8),%XMM4,%XMM4

    (327) 0x240079 VMOVHPD	(%R11,%R10,8),%XMM8,%XMM8

    (327) 0x24007f VMOVHPD	(%R11,%R9,8),%XMM2,%XMM2

    (327) 0x240085 VINSERTF128	$0x1,%XMM2,%YMM4,%YMM2

    (327) 0x24008b VMOVSD	(%R11,%R15,8),%XMM4

    (327) 0x240091 VMOVHPD	(%R11,%R13,8),%XMM4,%XMM4

    (327) 0x240097 VINSERTF128	$0x1,%XMM4,%YMM8,%YMM4

    (327) 0x24009d VMOVAPD	%YMM28,%YMM8

    (327) 0x2400a3 VFMADD213PD	%YMM29,%YMM12,%YMM8

    (327) 0x2400a9 VFMADD213PD	%YMM10,%YMM9,%YMM12

    (327) 0x2400ae VFMADD213PD	%YMM7,%YMM4,%YMM20

    (327) 0x2400b4 VFMADD231PD	%YMM27,%YMM16,%YMM8

    (327) 0x2400ba VFMADD231PD	%YMM16,%YMM31,%YMM12

    (327) 0x2400c0 VFMADD231PD	%YMM26,%YMM14,%YMM8

    (327) 0x2400c6 VFMADD231PD	%YMM14,%YMM30,%YMM12

    (327) 0x2400cc VFMADD213PD	%YMM5,%YMM2,%YMM8

    (327) 0x2400d1 VPBROADCASTD	-0x3c006(%RIP),%XMM2

    (327) 0x2400da VMOVAPD	%YMM11,%YMM5

    (327) 0x2400de VPADDD	%XMM2,%XMM1,%XMM1

    (327) 0x2400e2 VPADDD	%XMM2,%XMM0,%XMM0

    (327) 0x2400e6 VPMOVSXDQ	%XMM1,%YMM1

    (327) 0x2400eb VPMOVSXDQ	%XMM0,%YMM0

    (327) 0x2400f0 VMOVQ	%XMM1,%RCX

    (327) 0x2400f5 VPEXTRQ	$0x1,%XMM1,%RDI

    (327) 0x2400fb VEXTRACTI128	$0x1,%YMM1,%XMM1

    (327) 0x240101 VMOVQ	%XMM0,%R10

    (327) 0x240106 VPEXTRQ	$0x1,%XMM0,%R14

    (327) 0x24010c VEXTRACTI128	$0x1,%YMM0,%XMM0

    (327) 0x240112 VMOVQ	%XMM1,%R9

    (327) 0x240117 VPEXTRQ	$0x1,%XMM1,%R8

    (327) 0x24011d VMOVSD	(%R11,%RCX,8),%XMM1

    (327) 0x240123 VMOVQ	%XMM0,%R15

    (327) 0x240128 VPEXTRQ	$0x1,%XMM0,%R13

    (327) 0x24012e VMOVSD	(%R11,%R10,8),%XMM2

    (327) 0x240134 VMOVSD	(%R11,%R9,8),%XMM0

    (327) 0x24013a VMOVHPD	(%R11,%RDI,8),%XMM1,%XMM1

    (327) 0x240140 VMOVHPD	(%R11,%R14,8),%XMM2,%XMM2

    (327) 0x240146 VMOVHPD	(%R11,%R8,8),%XMM0,%XMM0

    (327) 0x24014c VINSERTF128	$0x1,%XMM0,%YMM1,%YMM0

    (327) 0x240152 VMOVSD	(%R11,%R15,8),%XMM1

    (327) 0x240158 VMOVHPD	(%R11,%R13,8),%XMM1,%XMM1

    (327) 0x24015e VINSERTF128	$0x1,%XMM1,%YMM2,%YMM1

    (327) 0x240164 VMOVAPD	%YMM12,%YMM2

    (327) 0x240168 VFMADD213PD	%YMM8,%YMM0,%YMM2

    (327) 0x24016d VFMADD213PD	%YMM20,%YMM1,%YMM5

    (327) 0x240173 CMP	%RDX,%R12

    (327) 0x240176 JNE	23fe20

  (325) 0x24017c VADDPD	%YMM2,%YMM5,%YMM0

  (325) 0x240180 VMOVSD	0x70(%RSP),%XMM14

  (325) 0x240186 VMOVDQA64	0x180(%RSP),%ZMM15

  (325) 0x24018e VMOVAPD	0x150(%RSP),%XMM16

  (325) 0x240196 VMOVAPD	0x160(%RSP),%YMM19

  (325) 0x24019e VMOVAPD	0x140(%RSP),%XMM20

  (325) 0x2401a6 VMOVAPD	0x130(%RSP),%XMM21

  (325) 0x2401ae VMOVAPD	0x120(%RSP),%XMM17

  (325) 0x2401b6 VMOVAPD	0x110(%RSP),%XMM18

  (325) 0x2401be VMOVAPD	0x100(%RSP),%XMM4

  (325) 0x2401c7 VMOVAPD	0xf0(%RSP),%XMM5

  (325) 0x2401d0 VMOVAPD	0xe0(%RSP),%XMM7

  (325) 0x2401d9 VMOVAPD	0xd0(%RSP),%XMM2

  (325) 0x2401e2 VMOVAPD	0xc0(%RSP),%XMM8

  (325) 0x2401eb VMOVAPD	0xb0(%RSP),%XMM9

  (325) 0x2401f4 VMOVAPD	0xa0(%RSP),%XMM10

  (325) 0x2401fd VMOVAPD	0x90(%RSP),%XMM11

  (325) 0x240206 MOV	0x68(%RSP),%R8

  (325) 0x24020b MOV	0x60(%RSP),%R9

  (325) 0x240210 MOV	0x58(%RSP),%R10

  (325) 0x240215 MOV	0x3c(%RSP),%R15D

  (325) 0x24021a MOV	0x48(%RSP),%R12

  (325) 0x24021f MOV	$0,%R14D

  (325) 0x240225 VEXTRACTF128	$0x1,%YMM0,%XMM1

  (325) 0x24022b VADDPD	%XMM1,%XMM0,%XMM0

  (325) 0x24022f VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (325) 0x240234 VADDSD	%XMM1,%XMM0,%XMM0

  (325) 0x240238 CMP	%RAX,%RBX

  (325) 0x24023b JE	23fb50

  (325) 0x240241 VUNPCKLPD	%XMM10,%XMM2,%XMM1

  (325) 0x240246 VUNPCKLPD	%XMM9,%XMM5,%XMM5

  (325) 0x24024b VUNPCKLPD	%XMM11,%XMM8,%XMM2

  (325) 0x240250 VUNPCKLPD	%XMM7,%XMM4,%XMM9

  (325) 0x240254 NOPW	%CS:(%RAX,%RAX,1)

    (328) 0x240260 VMULSD	(%RSI,%RBX,8),%XMM16,%XMM3

    (328) 0x240267 INC	%RBX

    (328) 0x24026a VROUNDSD	$0xb,%XMM3,%XMM3,%XMM4

    (328) 0x240270 VCVTTSD2SI	%XMM3,%ECX

    (328) 0x240274 MOVSXD	%ECX,%RDX

    (328) 0x240277 VSUBSD	%XMM4,%XMM3,%XMM3

    (328) 0x24027b VMOVAPD	%XMM20,%XMM4

    (328) 0x240281 VMULSD	%XMM3,%XMM3,%XMM8

    (328) 0x240285 VMOVDDUP	%XMM3,%XMM7

    (328) 0x240289 VFMADD213SD	%XMM21,%XMM3,%XMM4

    (328) 0x24028f VFMADD213PD	%XMM2,%XMM1,%XMM7

    (328) 0x240294 VMULSD	%XMM3,%XMM8,%XMM10

    (328) 0x240298 VMOVDDUP	%XMM8,%XMM8

    (328) 0x24029d VFMADD213SD	%XMM18,%XMM17,%XMM3

    (328) 0x2402a3 VMOVDDUP	%XMM10,%XMM10

    (328) 0x2402a8 VFMADD231PD	%XMM8,%XMM5,%XMM7

    (328) 0x2402ad VUNPCKLPD	%XMM8,%XMM10,%XMM11

    (328) 0x2402b2 VMULPD	%XMM19,%XMM11,%XMM12

    (328) 0x2402b8 VMULPD	%XMM6,%XMM11,%XMM8

    (328) 0x2402bc VFMADD231PD	%XMM10,%XMM9,%XMM7

    (328) 0x2402c1 VMULPD	0x8(%R11,%RDX,8),%XMM7,%XMM7

    (328) 0x2402c8 VADDSD	%XMM4,%XMM12,%XMM4

    (328) 0x2402cc VSHUFPD	$0x1,%XMM12,%XMM12,%XMM13

    (328) 0x2402d2 VADDSD	%XMM3,%XMM8,%XMM3

    (328) 0x2402d6 VSHUFPD	$0x1,%XMM8,%XMM8,%XMM10

    (328) 0x2402dc VADDSD	%XMM4,%XMM13,%XMM4

    (328) 0x2402e0 VFMADD132SD	(%R11,%RDX,8),%XMM0,%XMM4

    (328) 0x2402e6 VADDSD	%XMM3,%XMM10,%XMM3

    (328) 0x2402ea VSHUFPD	$0x1,%XMM7,%XMM7,%XMM0

    (328) 0x2402ef VADDSD	%XMM0,%XMM7,%XMM0

    (328) 0x2402f3 VADDSD	%XMM0,%XMM4,%XMM0

    (328) 0x2402f7 VFMADD231SD	0x18(%R11,%RDX,8),%XMM3,%XMM0

    (328) 0x2402fe CMP	%RBX,%RAX

    (328) 0x240301 JNE	240260

  (325) 0x240307 JMP	23fb50

0x24030c LEA	-0x28(%RBP),%RSP

0x240310 POP	%RBX

0x240311 POP	%R12

0x240313 POP	%R13

0x240315 POP	%R14

0x240317 POP	%R15

0x240319 POP	%RBP

0x24031a RET

0x24031b CALL	241420 <_ZSt27__throw_bad_optional_accessv>

Coverage (%)	Name	Source Location	Module
►96.14+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:272	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.omp_outlined.64	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.02+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:272	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.omp_outlined.64	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	main	miniqmc.cpp:411	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	TwoBodyJastrowRef.h:106-132
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/optional:433,950-952
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:106-109,126-132
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:236-260
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046,1064
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/refwrap.h:338
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 3.63 to 0.25 cycles (14.22x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

std::__throw_bad_optional_access(): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/optional:952

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	32
nb uops	29
loop length	117
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.63 cycles
front end	3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.33	1.33	1.33	1.33	1.33	1.33	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.33	1.33	1.33	1.33	1.33	1.33	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.63
Dispatch	1.75
Overall L1	3.63

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.63 cycles. At this rate:

1% of peak load performance is reached (4.41 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.83 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.63 to 1.75 cycles (2.07x speedup).

ASM code

In the binary file, the address of the function is: 23f9d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x200,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RAX,(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
JE 24030c <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x93c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RDI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RSI,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RAX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 23fa5b <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x8b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
CALL 241420 <_ZSt27__throw_bad_optional_accessv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	TwoBodyJastrowRef.h:106-132
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/optional:433,950-952
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:106-109,126-132
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:236-260
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046,1064
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/refwrap.h:338
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

std::__throw_bad_optional_access(): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/optional:952

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	32
nb uops	29
loop length	117
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.63 cycles
front end	3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.33	1.33	1.33	1.33	1.33	1.33	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.33	1.33	1.33	1.33	1.33	1.33	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.63
Dispatch	1.75
Overall L1	3.63

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.63 cycles. At this rate:

1% of peak load performance is reached (4.41 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.83 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 23f9d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x200,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x8(%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RAX,(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
JE 24030c <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x93c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RDI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RSI,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RAX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 23fa5b <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x8b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
CALL 241420 <_ZSt27__throw_bad_optional_accessv>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::TwoBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)–	1.08	1.79
▼Loop 324 - TwoBodyJastrowRef.h:107-132 - exec–	0.01	0.01
▼Loop 325 - BsplineFunctor.h:236-260 - exec–	0.02	0.02
○Loop 326 - BsplineFunctor.h:236-241 - exec	1.01	1.67
○Loop 327 - BsplineFunctor.h:246-260 - exec	0.04	0.07
○Loop 328 - BsplineFunctor.h:246-260 - exec	0.01	0.01
○Loop 329 - BsplineFunctor.h:236-241 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code