OV - exec - Function qmcplusplus::Vector<double, std::allocator<double> >::resize(unsigned long, double)

	Function: qmcplusplus::Vector<double, std::allocator<double> >::resize(unsigned long, double)	Module: exec	Source: OhmmsVector.h:182-302 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h: 111 - 145

--------------------------------------------------------------------------------

111: 	if (__builtin_expect(__n > this->_M_max_size(), false))

112: 	  {

113: 	    // _GLIBCXX_RESOLVE_LIB_DEFECTS

114: 	    // 3190. allocator::allocate sometimes returns too little storage

115: 	    if (__n > (std::size_t(-1) / sizeof(_Tp)))

116: 	      std::__throw_bad_array_new_length();

117: 	    std::__throw_bad_alloc();

[...]

127: 	return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp)));

[...]

145: 	::operator delete(__p

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 923 - 1120

--------------------------------------------------------------------------------

923:       for (; __first != __last; ++__first)

924: 	*__first = __tmp;

[...]

1120:       std::__fill_a(__first, __first + __n, __value);

/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 182 - 302

--------------------------------------------------------------------------------

182:   {

183:     static_assert(std::is_same<value_type, typename Alloc::value_type>::value,

184:                   "Vector and Alloc data types must agree!");

185:     if (nLocal > nAllocated)

186:       throw std::runtime_error("Resize not allowed on Vector constructed by initialized memory.");

187:

188:     if (n > nAllocated)

[...]

195:       if (n > nLocal)

196:         qmc_allocator_traits<Alloc>::fill_n(X + nLocal, n - nLocal, val);

197:       nLocal = n;

198:     }

199:     return;

[...]

296:     if (nAllocated)

297:     {

298:       mAllocator.deallocate(X, nAllocated);

299:     }

300:     X          = mAllocator.allocate(n);

301:     nLocal     = n;

302:     nAllocated = n;

0x239950 PUSH	%RBP

0x239951 MOV	%RSP,%RBP

0x239954 PUSH	%R15

0x239956 PUSH	%R14

0x239958 PUSH	%RBX

0x239959 SUB	$0x18,%RSP

0x23995d MOV	0x8(%RDI),%R8

0x239961 MOV	0x10(%RDI),%RAX

0x239965 CMP	%RAX,%R8

0x239968 JA	239baf

0x23996e MOV	%RSI,%RBX

0x239971 MOV	%RDI,%R14

0x239974 CMP	%RSI,%RAX

0x239977 JAE	2399d6

0x239979 VMOVAPS	%XMM0,-0x30(%RBP)

0x23997e TEST	%RAX,%RAX

0x239981 JE	23998c

0x239983 MOV	0x18(%R14),%RDI

0x239987 CALL	2f6c70 <@plt_start@+0x30>

0x23998c MOV	%RBX,%RAX

0x23998f MOV	$0x1fffffffffffffff,%R15

0x239999 SHR	$0x3c,%RAX

0x23999d JNE	239ba0

0x2399a3 LEA	(,%RBX,8),%RDI

0x2399ab CALL	2f6c50 <@plt_start@+0x10>

0x2399b0 LEA	(%RBX,%R15,1),%RSI

0x2399b4 MOV	%RAX,0x18(%R14)

0x2399b8 MOV	%RBX,0x8(%R14)

0x2399bc MOV	%RBX,0x10(%R14)

0x2399c0 AND	%R15,%RSI

0x2399c3 CMP	$0x3,%RSI

0x2399c7 JAE	239a08

0x2399c9 VMOVAPS	-0x30(%RBP),%XMM1

0x2399ce MOV	%RAX,%RDI

0x2399d1 JMP	239b59

0x2399d6 CMP	%RBX,%R8

0x2399d9 JAE	239b8e

0x2399df MOV	0x18(%R14),%RAX

0x2399e3 LEA	(,%RBX,8),%RDI

0x2399eb LEA	(%RAX,%R8,8),%RCX

0x2399ef SAL	$0x3,%R8

0x2399f3 SUB	%R8,%RDI

0x2399f6 ADD	$-0x8,%RDI

0x2399fa CMP	$0x18,%RDI

0x2399fe JAE	239a25

0x239a00 MOV	%RCX,%R8

0x239a03 JMP	239b73

0x239a08 VMOVAPS	-0x30(%RBP),%XMM1

0x239a0d LEA	0x1(%RSI),%RCX

0x239a11 MOV	$0x3fffffffffffffe0,%RDX

0x239a1b CMP	$0x1f,%RSI

0x239a1f JAE	239a4d

0x239a21 XOR	%ESI,%ESI

0x239a23 JMP	239a9a

0x239a25 MOV	%RDI,%RDX

0x239a28 SHR	$0x3,%RDX

0x239a2c MOV	$0x3fffffffffffffe0,%RSI

0x239a36 INC	%RDX

0x239a39 CMP	$0xf8,%RDI

0x239a40 JAE	239acc

0x239a46 XOR	%EDI,%EDI

0x239a48 JMP	239b22

0x239a4d VBROADCASTSD	%XMM1,%ZMM0

0x239a53 MOV	%RCX,%RSI

0x239a56 AND	%RDX,%RSI

0x239a59 XOR	%EDI,%EDI

0x239a5b NOPL	(%RAX,%RAX,1)

(236) 0x239a60 VMOVUPS	%ZMM0,(%RAX,%RDI,8)

(236) 0x239a67 VMOVUPS	%ZMM0,0x40(%RAX,%RDI,8)

(236) 0x239a6f VMOVUPS	%ZMM0,0x80(%RAX,%RDI,8)

(236) 0x239a77 VMOVUPS	%ZMM0,0xc0(%RAX,%RDI,8)

(236) 0x239a7f ADD	$0x20,%RDI

(236) 0x239a83 CMP	%RDI,%RSI

(236) 0x239a86 JNE	239a60

0x239a88 CMP	%RSI,%RCX

0x239a8b JE	239b92

0x239a91 TEST	$0x1c,%CL

0x239a94 JE	239b55

0x239a9a ADD	$0x1c,%RDX

0x239a9e VBROADCASTSD	%XMM1,%YMM0

0x239aa3 AND	%RCX,%RDX

0x239aa6 LEA	(%RAX,%RDX,8),%RDI

0x239aaa NOPW	(%RAX,%RAX,1)

(238) 0x239ab0 VMOVUPS	%YMM0,(%RAX,%RSI,8)

(238) 0x239ab5 ADD	$0x4,%RSI

(238) 0x239ab9 CMP	%RSI,%RDX

(238) 0x239abc JNE	239ab0

0x239abe CMP	%RDX,%RCX

0x239ac1 JNE	239b59

0x239ac7 JMP	239b92

0x239acc VBROADCASTSD	%XMM0,%ZMM1

0x239ad2 LEA	0xc0(%R8,%RAX,1),%R8

0x239ada MOV	%RDX,%RDI

0x239add AND	%RSI,%RDI

0x239ae0 XOR	%R9D,%R9D

0x239ae3 NOPW	%CS:(%RAX,%RAX,1)

(233) 0x239af0 VMOVUPS	%ZMM1,-0xc0(%R8,%R9,8)

(233) 0x239af8 VMOVUPS	%ZMM1,-0x80(%R8,%R9,8)

(233) 0x239b00 VMOVUPS	%ZMM1,-0x40(%R8,%R9,8)

(233) 0x239b08 VMOVUPS	%ZMM1,(%R8,%R9,8)

(233) 0x239b0f ADD	$0x20,%R9

(233) 0x239b13 CMP	%R9,%RDI

(233) 0x239b16 JNE	239af0

0x239b18 CMP	%RDI,%RDX

0x239b1b JE	239b8e

0x239b1d TEST	$0x1c,%DL

0x239b20 JE	239b6f

0x239b22 ADD	$0x1c,%RSI

0x239b26 VBROADCASTSD	%XMM0,%YMM1

0x239b2b AND	%RDX,%RSI

0x239b2e LEA	(%RCX,%RSI,8),%R8

0x239b32 NOPW	%CS:(%RAX,%RAX,1)

(235) 0x239b40 VMOVUPS	%YMM1,(%RCX,%RDI,8)

(235) 0x239b45 ADD	$0x4,%RDI

(235) 0x239b49 CMP	%RDI,%RSI

(235) 0x239b4c JNE	239b40

0x239b4e CMP	%RSI,%RDX

0x239b51 JNE	239b73

0x239b53 JMP	239b8e

0x239b55 LEA	(%RAX,%RSI,8),%RDI

0x239b59 LEA	(%RAX,%RBX,8),%RAX

0x239b5d NOPL	(%RAX)

(237) 0x239b60 VMOVSD	%XMM1,(%RDI)

(237) 0x239b64 ADD	$0x8,%RDI

(237) 0x239b68 CMP	%RAX,%RDI

(237) 0x239b6b JNE	239b60

0x239b6d JMP	239b92

0x239b6f LEA	(%RCX,%RDI,8),%R8

0x239b73 LEA	(%RAX,%RBX,8),%RAX

0x239b77 NOPW	(%RAX,%RAX,1)

(234) 0x239b80 VMOVSD	%XMM0,(%R8)

(234) 0x239b85 ADD	$0x8,%R8

(234) 0x239b89 CMP	%RAX,%R8

(234) 0x239b8c JNE	239b80

0x239b8e MOV	%RBX,0x8(%R14)

0x239b92 ADD	$0x18,%RSP

0x239b96 POP	%RBX

0x239b97 POP	%R14

0x239b99 POP	%R15

0x239b9b POP	%RBP

0x239b9c VZEROUPPER

0x239b9f RET

0x239ba0 CMP	%R15,%RBX

0x239ba3 JBE	239baa

0x239ba5 CALL	2f6e40 <@plt_start@+0x200>

0x239baa CALL	2f6fc0 <@plt_start@+0x380>

0x239baf MOV	$0x10,%EDI

0x239bb4 CALL	2f6e70 <@plt_start@+0x230>

0x239bb9 MOV	%RAX,%RBX

0x239bbc LEA	-0x3341f(%RIP),%RSI

0x239bc3 MOV	%RAX,%RDI

0x239bc6 CALL	2f6e80 <@plt_start@+0x240>

0x239bcb MOV	0xc2d06(%RIP),%RSI

0x239bd2 MOV	0xc2d07(%RIP),%RDX

0x239bd9 MOV	%RBX,%RDI

0x239bdc CALL	2f6e90 <@plt_start@+0x250>

0x239be1 MOV	%RBX,%RDI

0x239be4 MOV	%RAX,%R14

0x239be7 CALL	2f6ea0 <@plt_start@+0x260>

0x239bec MOV	%R14,%RDI

0x239bef CALL	2f6c90 <@plt_start@+0x50>

0x239bf4 INT	$0x3

0x239bf5 INT	$0x3

0x239bf6 INT	$0x3

0x239bf7 INT	$0x3

0x239bf8 INT	$0x3

0x239bf9 INT	$0x3

0x239bfa INT	$0x3

0x239bfb INT	$0x3

0x239bfc INT	$0x3

0x239bfd INT	$0x3

0x239bfe INT	$0x3

0x239bff INT	$0x3

Coverage (%)	Name	Source Location	Module
►19.62+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:70	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:80	exec
○	main.omp_outlined	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►17.18+	miniqmcreference::DiracDetermi[...]	TinyVector.h:62	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:80	exec
○	main.omp_outlined	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►16.96+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:70	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:81	exec
○	main.omp_outlined	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►16.24+	miniqmcreference::DiracDetermi[...]	TinyVector.h:62	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:81	exec
○	main.omp_outlined	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►14.47+	miniqmcreference::DiracDetermi[...]	OhmmsMatrix.h:104	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:80	exec
○	main.omp_outlined	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►12.47+	miniqmcreference::DiracDetermi[...]	OhmmsMatrix.h:104	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:48	exec
○	qmcplusplus::build_WaveFunctio[...]	WaveFunction.cpp:81	exec
○	main.omp_outlined	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	OhmmsVector.h:182-302
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:111-117,127,145
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923-924,1120
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:182-188,195-199,296-302

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.88 to 5.33 cycles (3.16x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 16.88 to 1.31 cycles (12.93x speedup).

Details

14% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

20% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
5% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

@plt_start@: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:127
unknown: 8 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:116
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:117
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	143
nb uops	135
loop length	553
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	2
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.88 cycles
front end	16.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	13.33	13.33	13.33	13.33	13.33	13.33	5.75	5.75	5.75	5.75	0.00	2.00	2.00	0.00	0.50	0.50
cycles	13.33	13.33	13.33	13.33	13.33	13.33	5.75	5.75	5.75	5.75	0.00	2.00	2.00	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.88
Dispatch	13.33
Overall L1	16.88

Vectorization ratios

INT

all	5%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	42%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	14%
load	100%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	17%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	14%
load	25%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.88 cycles. At this rate:

1% of peak load performance is reached (4.74 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.84 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.88 to 13.33 cycles (1.27x speedup).

ASM code

In the binary file, the address of the function is: 239950

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x8(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 239baf <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x25f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 2399d6 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x86>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVAPS %XMM0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 23998c <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x3c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CALL 2f6c70 <@plt_start@+0x30>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x1fffffffffffffff,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3c,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JNE 239ba0 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x250>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%RBX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL 2f6c50 <@plt_start@+0x10>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA (%RBX,%R15,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,0x18(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x8(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x10(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x3,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 239a08 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xb8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVAPS -0x30(%RBP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 239b59 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x209>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
CMP %RBX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 239b8e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x23e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (,%RBX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R8,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $-0x8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x18,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 239a25 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xd5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 239b73 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x223>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS -0x30(%RBP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
LEA 0x1(%RSI),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x3fffffffffffffe0,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x1f,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 239a4d <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xfd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 239a9a <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x14a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x3fffffffffffffe0,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0xf8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 239acc <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x17c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 239b22 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1d2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VBROADCASTSD %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 239b92 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x242>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST $0x1c,%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 239b55 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x205>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x1c,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
AND %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 239b59 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x209>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 239b92 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x242>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VBROADCASTSD %XMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
LEA 0xc0(%R8,%RAX,1),%R8	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND %RSI,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 239b8e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x23e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST $0x1c,%DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 239b6f <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x21f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x1c,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSD %XMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
AND %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RCX,%RSI,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RSI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 239b73 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x223>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 239b8e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x23e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
LEA (%RAX,%RSI,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RBX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 239b92 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x242>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
LEA (%RCX,%RDI,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RBX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RBX,0x8(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP %R15,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JBE 239baa <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x25a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CALL 2f6e40 <@plt_start@+0x200>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CALL 2f6fc0 <@plt_start@+0x380>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV $0x10,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 2f6e70 <@plt_start@+0x230>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x3341f(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2f6e80 <@plt_start@+0x240>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0xc2d06(%RIP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc2d07(%RIP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2f6e90 <@plt_start@+0x250>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2f6ea0 <@plt_start@+0x260>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2f6c90 <@plt_start@+0x50>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	OhmmsVector.h:182-302
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:111-117,127,145
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923-924,1120
/home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:182-188,195-199,296-302

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.88 to 5.33 cycles (3.16x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

14% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

20% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
5% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

@plt_start@: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:127
unknown: 8 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:145
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:116
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:117
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186
- /home/eoseret/qaas_runs_ZEN5/173-938-0042/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:186

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	143
nb uops	135
loop length	553
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	2
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.88 cycles
front end	16.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	13.33	13.33	13.33	13.33	13.33	13.33	5.75	5.75	5.75	5.75	0.00	2.00	2.00	0.00	0.50	0.50
cycles	13.33	13.33	13.33	13.33	13.33	13.33	5.75	5.75	5.75	5.75	0.00	2.00	2.00	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.88
Dispatch	13.33
Overall L1	16.88

Vectorization ratios

INT

all	5%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	42%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	14%
load	100%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	17%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	14%
load	25%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.88 cycles. At this rate:

1% of peak load performance is reached (4.74 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.84 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 239950

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x8(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 239baf <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x25f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 2399d6 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x86>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVAPS %XMM0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 23998c <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x3c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CALL 2f6c70 <@plt_start@+0x30>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x1fffffffffffffff,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3c,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JNE 239ba0 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x250>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%RBX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL 2f6c50 <@plt_start@+0x10>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA (%RBX,%R15,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,0x18(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x8(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x10(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x3,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 239a08 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xb8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVAPS -0x30(%RBP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 239b59 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x209>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
CMP %RBX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 239b8e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x23e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (,%RBX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R8,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $-0x8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x18,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 239a25 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xd5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 239b73 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x223>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS -0x30(%RBP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
LEA 0x1(%RSI),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x3fffffffffffffe0,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x1f,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 239a4d <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xfd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 239a9a <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x14a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x3fffffffffffffe0,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0xf8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 239acc <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x17c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 239b22 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1d2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VBROADCASTSD %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 239b92 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x242>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST $0x1c,%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 239b55 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x205>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x1c,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
AND %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 239b59 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x209>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 239b92 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x242>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VBROADCASTSD %XMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
LEA 0xc0(%R8,%RAX,1),%R8	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND %RSI,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 239b8e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x23e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST $0x1c,%DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 239b6f <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x21f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x1c,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSD %XMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
AND %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RCX,%RSI,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RSI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 239b73 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x223>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 239b8e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x23e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
LEA (%RAX,%RSI,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RBX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 239b92 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x242>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
LEA (%RCX,%RDI,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RBX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RBX,0x8(%R14)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP %R15,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JBE 239baa <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x25a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CALL 2f6e40 <@plt_start@+0x200>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CALL 2f6fc0 <@plt_start@+0x380>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV $0x10,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 2f6e70 <@plt_start@+0x230>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x3341f(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2f6e80 <@plt_start@+0x240>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0xc2d06(%RIP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc2d07(%RIP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2f6e90 <@plt_start@+0x250>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2f6ea0 <@plt_start@+0x260>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2f6c90 <@plt_start@+0x50>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A
INT $0x3																				N/A

Name	Coverage (%)	Time (s)
▼qmcplusplus::Vector >::resize(unsigned long, double)–	0.02	0.04
○Loop 236 - stl_algobase.h:924-924 - exec	0.02	0.04
○Loop 238 - stl_algobase.h:924-924 - exec	0.00	0.00
○Loop 234 - stl_algobase.h:923-924 - exec	0.00	0.00
○Loop 233 - stl_algobase.h:924-924 - exec	0.00	0.00
○Loop 235 - stl_algobase.h:924-924 - exec	0.00	0.00
○Loop 237 - stl_algobase.h:923-924 - exec	0.00	0.00

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