OV - - Loop 990

	Loop Id: 990	Module: exec	Source: inner_product.hpp:155-155 [...]	Coverage: 0.16%

0x496d4d VMOVUPD	(%RAX),%ZMM9    [1]

0x496d53 VMOVUPD	0x100(%RAX),%ZMM31    [1]

0x496d5a VMOVUPD	(%RAX),%ZMM2    [1]

0x496d60 ADD	$0x100,%RCX

0x496d67 VMOVUPD	0xc0(%RAX),%ZMM20    [1]

0x496d6e VMOVUPD	0xc0(%RAX),%ZMM10    [1]

0x496d75 VMOVUPD	0x1c0(%RAX),%ZMM25    [1]

0x496d7c ADD	$0x300,%RAX

0x496d82 VMOVUPD	-0x300(%RAX),%ZMM28    [2]

0x496d89 VMOVUPD	-0x240(%RAX),%ZMM22    [2]

0x496d90 VMOVUPD	-0x100(%RAX),%ZMM23    [2]

0x496d97 VMOVUPD	-0x40(%RAX),%ZMM27    [2]

0x496d9e VPERMT2PD	-0x2c0(%RAX),%ZMM6,%ZMM9    [2]

0x496da5 VPERMT2PD	-0x2c0(%RAX),%ZMM4,%ZMM2    [2]

0x496dac VPERMT2PD	-0x280(%RAX),%ZMM5,%ZMM9    [2]

0x496db3 VFMADD132PD	-0x100(%RCX),%ZMM24,%ZMM9    [3]

0x496dba VMOVUPD	-0x1c0(%RAX),%ZMM24    [2]

0x496dc1 VPERMT2PD	%ZMM31,%ZMM6,%ZMM20

0x496dc7 VPERMT2PD	%ZMM31,%ZMM4,%ZMM10

0x496dcd VPERMT2PD	-0x280(%RAX),%ZMM3,%ZMM2    [2]

0x496dd4 VFMADD231PD	-0x100(%RCX),%ZMM2,%ZMM0    [3]

0x496ddb VMOVUPD	-0x180(%RAX),%ZMM2    [2]

0x496de2 VPERMT2PD	-0x2c0(%RAX),%ZMM8,%ZMM28    [2]

0x496de9 VPERMT2PD	%ZMM31,%ZMM8,%ZMM22

0x496def VPERMT2PD	-0x280(%RAX),%ZMM7,%ZMM28    [2]

0x496df6 VFMADD132PD	-0x100(%RCX),%ZMM30,%ZMM28    [3]

0x496dfd VMOVUPD	-0x80(%RAX),%ZMM30    [2]

0x496e04 VPERMT2PD	%ZMM24,%ZMM5,%ZMM20

0x496e0a VPERMT2PD	%ZMM24,%ZMM3,%ZMM10

0x496e10 VFMADD132PD	-0xc0(%RCX),%ZMM9,%ZMM20    [3]

0x496e17 VFMADD132PD	-0xc0(%RCX),%ZMM0,%ZMM10    [3]

0x496e1e VMOVUPD	-0x180(%RAX),%ZMM9    [2]

0x496e25 VMOVUPD	-0x180(%RAX),%ZMM0    [2]

0x496e2c VPERMT2PD	%ZMM24,%ZMM7,%ZMM22

0x496e32 VMOVAPD	%ZMM10,%ZMM26

0x496e38 VPERMT2PD	%ZMM25,%ZMM6,%ZMM2

0x496e3e VFMADD132PD	-0xc0(%RCX),%ZMM28,%ZMM22    [3]

0x496e45 VMOVUPD	-0xc0(%RAX),%ZMM24    [2]

0x496e4c VPERMT2PD	%ZMM23,%ZMM5,%ZMM2

0x496e52 VFMADD132PD	-0x80(%RCX),%ZMM20,%ZMM2    [3]

0x496e59 VPERMT2PD	%ZMM25,%ZMM8,%ZMM9

0x496e5f VPERMT2PD	%ZMM25,%ZMM4,%ZMM0

0x496e65 VPERMT2PD	%ZMM23,%ZMM3,%ZMM0

0x496e6b VPERMT2PD	%ZMM23,%ZMM7,%ZMM9

0x496e71 VFMADD231PD	-0x80(%RCX),%ZMM0,%ZMM26    [3]

0x496e78 VFMADD132PD	-0x80(%RCX),%ZMM22,%ZMM9    [3]

0x496e7f VMOVUPD	-0xc0(%RAX),%ZMM22    [2]

0x496e86 VPERMT2PD	%ZMM30,%ZMM6,%ZMM24

0x496e8c VMOVUPD	-0xc0(%RAX),%ZMM0    [2]

0x496e93 VPERMT2PD	%ZMM27,%ZMM5,%ZMM24

0x496e99 VFMADD132PD	-0x40(%RCX),%ZMM2,%ZMM24    [3]

0x496ea0 VPERMT2PD	%ZMM30,%ZMM8,%ZMM22

0x496ea6 VPERMT2PD	%ZMM30,%ZMM4,%ZMM0

0x496eac VPERMT2PD	%ZMM27,%ZMM7,%ZMM22

0x496eb2 VPERMT2PD	%ZMM27,%ZMM3,%ZMM0

0x496eb8 VFMADD132PD	-0x40(%RCX),%ZMM9,%ZMM22    [3]

0x496ebf VFMADD132PD	-0x40(%RCX),%ZMM26,%ZMM0    [3]

0x496ec6 VMOVAPD	%ZMM22,%ZMM30

0x496ecc CMP	%RCX,%R15

0x496ecf JNE	496d4d

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 155 - 155

--------------------------------------------------------------------------------

155:   for (int i = 0; i < n; i++)

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 63 - 94

--------------------------------------------------------------------------------

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.44
Bottlenecks	P5, P6, P7, P8, P9, P10,
Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb
Source	inner_product.hpp:155-155,OperatorTags.h:63-63,OperatorTags.h:94-94
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	24.00
Front-end cycles	9.83
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	24.00
P5 cycles	24.00
P6 cycles	24.00
P7 cycles	24.00
P8 cycles	24.00
P9 cycles	24.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	59.00
Nb loads	36.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	96.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	96.00
Bytes prefetched	0.00
Bytes loaded	2304.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.44
Bottlenecks	P5, P6, P7, P8, P9, P10,
Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb
Source	inner_product.hpp:155-155,OperatorTags.h:63-63,OperatorTags.h:94-94
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	24.00
Front-end cycles	9.83
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	24.00
P5 cycles	24.00
P6 cycles	24.00
P7 cycles	24.00
P8 cycles	24.00
P9 cycles	24.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	59.00
Nb loads	36.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	96.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	96.00
Bytes prefetched	0.00
Bytes loaded	2304.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb
Source file and lines	inner_product.hpp:155-155
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck)
reading data from caches/RAM (load units are a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 24.00 to 9.83 cycles (2.44x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions
Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 96 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

96: addition or subtraction (all inside FMA instructions)
96: multiply (all inside FMA instructions)

The binary loop is loading 2304 bytes (288 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	60
nb uops	59
loop length	392
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	20
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.83 cycles
front end	9.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	12.00	12.00	12.00	12.00	24.00	24.00	0.00	0.00	0.00
cycles	0.75	0.75	0.50	0.50	0.50	24.00	24.00	24.00	24.00	24.00	24.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	9.83
Dispatch	24.00
Data deps.	16.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

99% of peak load performance is reached (96.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 496d4d

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	Latency	Recip. throughput
VMOVUPD (%RAX),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0x100(%RAX),%ZMM31	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD (%RAX),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
ADD $0x100,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
VMOVUPD 0xc0(%RAX),%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0xc0(%RAX),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0x1c0(%RAX),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
ADD $0x300,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
VMOVUPD -0x300(%RAX),%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD -0x240(%RAX),%ZMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD -0x100(%RAX),%ZMM23	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD -0x40(%RAX),%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD -0x2c0(%RAX),%ZMM6,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VPERMT2PD -0x2c0(%RAX),%ZMM4,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VPERMT2PD -0x280(%RAX),%ZMM5,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VFMADD132PD -0x100(%RCX),%ZMM24,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x1c0(%RAX),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM31,%ZMM6,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM31,%ZMM4,%ZMM10	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD -0x280(%RAX),%ZMM3,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VFMADD231PD -0x100(%RCX),%ZMM2,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x180(%RAX),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD -0x2c0(%RAX),%ZMM8,%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VPERMT2PD %ZMM31,%ZMM8,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD -0x280(%RAX),%ZMM7,%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VFMADD132PD -0x100(%RCX),%ZMM30,%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x80(%RAX),%ZMM30	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM24,%ZMM5,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM24,%ZMM3,%ZMM10	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0xc0(%RCX),%ZMM9,%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VFMADD132PD -0xc0(%RCX),%ZMM0,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x180(%RAX),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD -0x180(%RAX),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM24,%ZMM7,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVAPD %ZMM10,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM25,%ZMM6,%ZMM2	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0xc0(%RCX),%ZMM28,%ZMM22	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0xc0(%RAX),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM23,%ZMM5,%ZMM2	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0x80(%RCX),%ZMM20,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VPERMT2PD %ZMM25,%ZMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM23,%ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM23,%ZMM7,%ZMM9	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD231PD -0x80(%RCX),%ZMM0,%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VFMADD132PD -0x80(%RCX),%ZMM22,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0xc0(%RAX),%ZMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM30,%ZMM6,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD -0xc0(%RAX),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM27,%ZMM5,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0x40(%RCX),%ZMM2,%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VPERMT2PD %ZMM30,%ZMM8,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM30,%ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM27,%ZMM7,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM27,%ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0x40(%RCX),%ZMM9,%ZMM22	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VFMADD132PD -0x40(%RCX),%ZMM26,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVAPD %ZMM22,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %RCX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JNE 496d4d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x55d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb
Source file and lines	inner_product.hpp:155-155
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck)
reading data from caches/RAM (load units are a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 24.00 to 9.83 cycles (2.44x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions
Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 96 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

96: addition or subtraction (all inside FMA instructions)
96: multiply (all inside FMA instructions)

The binary loop is loading 2304 bytes (288 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	60
nb uops	59
loop length	392
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	20
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.83 cycles
front end	9.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	12.00	12.00	12.00	12.00	24.00	24.00	0.00	0.00	0.00
cycles	0.75	0.75	0.50	0.50	0.50	24.00	24.00	24.00	24.00	24.00	24.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	9.83
Dispatch	24.00
Data deps.	16.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

99% of peak load performance is reached (96.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 496d4d

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	Latency	Recip. throughput
VMOVUPD (%RAX),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0x100(%RAX),%ZMM31	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD (%RAX),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
ADD $0x100,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
VMOVUPD 0xc0(%RAX),%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0xc0(%RAX),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0x1c0(%RAX),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
ADD $0x300,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
VMOVUPD -0x300(%RAX),%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD -0x240(%RAX),%ZMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD -0x100(%RAX),%ZMM23	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD -0x40(%RAX),%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD -0x2c0(%RAX),%ZMM6,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VPERMT2PD -0x2c0(%RAX),%ZMM4,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VPERMT2PD -0x280(%RAX),%ZMM5,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VFMADD132PD -0x100(%RCX),%ZMM24,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x1c0(%RAX),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM31,%ZMM6,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM31,%ZMM4,%ZMM10	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD -0x280(%RAX),%ZMM3,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VFMADD231PD -0x100(%RCX),%ZMM2,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x180(%RAX),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD -0x2c0(%RAX),%ZMM8,%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VPERMT2PD %ZMM31,%ZMM8,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD -0x280(%RAX),%ZMM7,%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VFMADD132PD -0x100(%RCX),%ZMM30,%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x80(%RAX),%ZMM30	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM24,%ZMM5,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM24,%ZMM3,%ZMM10	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0xc0(%RCX),%ZMM9,%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VFMADD132PD -0xc0(%RCX),%ZMM0,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x180(%RAX),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD -0x180(%RAX),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM24,%ZMM7,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVAPD %ZMM10,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM25,%ZMM6,%ZMM2	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0xc0(%RCX),%ZMM28,%ZMM22	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0xc0(%RAX),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM23,%ZMM5,%ZMM2	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0x80(%RCX),%ZMM20,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VPERMT2PD %ZMM25,%ZMM8,%ZMM9	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM23,%ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM23,%ZMM7,%ZMM9	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD231PD -0x80(%RCX),%ZMM0,%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VFMADD132PD -0x80(%RCX),%ZMM22,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0xc0(%RAX),%ZMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM30,%ZMM6,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD -0xc0(%RAX),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM27,%ZMM5,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0x40(%RCX),%ZMM2,%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VPERMT2PD %ZMM30,%ZMM8,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM30,%ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM27,%ZMM7,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM27,%ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0x40(%RCX),%ZMM9,%ZMM22	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VFMADD132PD -0x40(%RCX),%ZMM26,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVAPD %ZMM22,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %RCX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JNE 496d4d <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x55d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.52	0.1	0.39	0.1	0.13	0.18	0.04	0.25	0.01	0.28	0	0.25	0	0.28

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.07	0.16
2x2	4	0.52	0.78	1.5	0.11	0.2
2x4	8	0.39	0.88	2.25	0.09	0.17
2x8	16	0.13	0.54	4	0.14	0.21
2x16	32	0.04	0.37	8.25	0.24	0.26
2x32	64	0.01	0.16	16.5	0.49	0.28
2x64	128	0	0.09	32.5	1.05	0.25
2x96	192	0	0.06	48.5	1.6	0.28

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency