OV - - Loop 986

	Loop Id: 986	Module: exec	Source: inner_product.hpp:155-155 [...]	Coverage: 0.13%

0x495dbf VMOVUPD	(%R15),%ZMM9    [1]

0x495dc5 VMOVUPD	(%R15),%ZMM3    [1]

0x495dcb VMOVUPD	(%R15),%ZMM11    [1]

0x495dd1 ADD	$0x100,%RSI

0x495dd8 VMOVUPD	0x140(%R15),%ZMM12    [1]

0x495ddf VMOVUPD	0xc0(%R15),%ZMM13    [1]

0x495de6 VMOVUPD	0xc0(%R15),%ZMM1    [1]

0x495ded ADD	$0x300,%R15

0x495df4 VMOVUPD	-0x180(%R15),%ZMM10    [2]

0x495dfb VPERMT2PD	-0x2c0(%R15),%ZMM14,%ZMM9    [2]

0x495e02 VPERMT2PD	-0x2c0(%R15),%ZMM5,%ZMM3    [2]

0x495e09 VPERMT2PD	-0x2c0(%R15),%ZMM7,%ZMM11    [2]

0x495e10 VPERMT2PD	-0x280(%R15),%ZMM8,%ZMM9    [2]

0x495e17 VFMADD132PD	-0x100(%RSI),%ZMM15,%ZMM9    [3]

0x495e1e VMOVUPD	-0x200(%R15),%ZMM15    [2]

0x495e25 VPERMT2PD	-0x280(%R15),%ZMM4,%ZMM3    [2]

0x495e2c VFMADD132PD	-0x100(%RSI),%ZMM0,%ZMM3    [3]

0x495e33 VMOVUPD	-0x240(%R15),%ZMM0    [2]

0x495e3a VPERMT2PD	-0x280(%R15),%ZMM6,%ZMM11    [2]

0x495e41 VFMADD231PD	-0x100(%RSI),%ZMM11,%ZMM2    [3]

0x495e48 VMOVUPD	-0x180(%R15),%ZMM11    [2]

0x495e4f VPERMT2PD	%ZMM15,%ZMM14,%ZMM13

0x495e55 VPERMT2PD	%ZMM15,%ZMM7,%ZMM1

0x495e5b VPERMT2PD	%ZMM15,%ZMM5,%ZMM0

0x495e61 VMOVUPD	-0x100(%R15),%ZMM15    [2]

0x495e68 VPERMT2PD	%ZMM12,%ZMM6,%ZMM1

0x495e6e VFMADD132PD	-0xc0(%RSI),%ZMM2,%ZMM1    [3]

0x495e75 VPERMT2PD	%ZMM12,%ZMM4,%ZMM0

0x495e7b VFMADD132PD	-0xc0(%RSI),%ZMM3,%ZMM0    [3]

0x495e82 VMOVUPD	-0x140(%R15),%ZMM3    [2]

0x495e89 VMOVUPD	-0x180(%R15),%ZMM2    [2]

0x495e90 VPERMT2PD	%ZMM12,%ZMM8,%ZMM13

0x495e96 VFMADD132PD	-0xc0(%RSI),%ZMM9,%ZMM13    [3]

0x495e9d VMOVUPD	-0x40(%R15),%ZMM12    [2]

0x495ea4 VPERMT2PD	%ZMM3,%ZMM7,%ZMM11

0x495eaa VPERMT2PD	%ZMM3,%ZMM14,%ZMM10

0x495eb0 VPERMT2PD	%ZMM3,%ZMM5,%ZMM2

0x495eb6 VPERMT2PD	%ZMM15,%ZMM6,%ZMM11

0x495ebc VPERMT2PD	%ZMM15,%ZMM8,%ZMM10

0x495ec2 VMOVAPD	%ZMM11,%ZMM9

0x495ec8 VFMADD132PD	-0x80(%RSI),%ZMM13,%ZMM10    [3]

0x495ecf VFMADD132PD	-0x80(%RSI),%ZMM1,%ZMM9    [3]

0x495ed6 VMOVUPD	-0x80(%R15),%ZMM13    [2]

0x495edd VMOVUPD	-0xc0(%R15),%ZMM1    [2]

0x495ee4 VPERMT2PD	%ZMM15,%ZMM4,%ZMM2

0x495eea VMOVUPD	-0xc0(%R15),%ZMM15    [2]

0x495ef1 VFMADD132PD	-0x80(%RSI),%ZMM0,%ZMM2    [3]

0x495ef8 VMOVUPD	-0xc0(%R15),%ZMM0    [2]

0x495eff VPERMT2PD	%ZMM13,%ZMM7,%ZMM1

0x495f05 VPERMT2PD	%ZMM13,%ZMM14,%ZMM15

0x495f0b VPERMT2PD	%ZMM12,%ZMM6,%ZMM1

0x495f11 VPERMT2PD	%ZMM13,%ZMM5,%ZMM0

0x495f17 VPERMT2PD	%ZMM12,%ZMM8,%ZMM15

0x495f1d VPERMT2PD	%ZMM12,%ZMM4,%ZMM0

0x495f23 VFMADD132PD	-0x40(%RSI),%ZMM2,%ZMM0    [3]

0x495f2a VFMADD132PD	-0x40(%RSI),%ZMM10,%ZMM15    [3]

0x495f31 VMOVAPD	%ZMM1,%ZMM2

0x495f37 VFMADD132PD	-0x40(%RSI),%ZMM9,%ZMM2    [3]

0x495f3e CMP	%RSI,%R9

0x495f41 JNE	495dbf

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 155 - 155

--------------------------------------------------------------------------------

155:   for (int i = 0; i < n; i++)

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 63 - 94

--------------------------------------------------------------------------------

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.44
Bottlenecks	P5, P6, P7, P8, P9, P10,
Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi
Source	inner_product.hpp:155-155,OperatorTags.h:63-63,OperatorTags.h:94-94
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	24.00
Front-end cycles	9.83
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	24.00
P5 cycles	24.00
P6 cycles	24.00
P7 cycles	24.00
P8 cycles	24.00
P9 cycles	24.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	59.00
Nb loads	36.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	96.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	96.00
Bytes prefetched	0.00
Bytes loaded	2304.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.44
Bottlenecks	P5, P6, P7, P8, P9, P10,
Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi
Source	inner_product.hpp:155-155,OperatorTags.h:63-63,OperatorTags.h:94-94
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	24.00
Front-end cycles	9.83
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	24.00
P5 cycles	24.00
P6 cycles	24.00
P7 cycles	24.00
P8 cycles	24.00
P9 cycles	24.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	59.00
Nb loads	36.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	96.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	96.00
Bytes prefetched	0.00
Bytes loaded	2304.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi
Source file and lines	inner_product.hpp:155-155
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck)
reading data from caches/RAM (load units are a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 24.00 to 9.83 cycles (2.44x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions
Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 96 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

96: addition or subtraction (all inside FMA instructions)
96: multiply (all inside FMA instructions)

The binary loop is loading 2304 bytes (288 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	60
nb uops	59
loop length	392
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.83 cycles
front end	9.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	12.00	12.00	12.00	12.00	24.00	24.00	0.00	0.00	0.00
cycles	0.75	0.75	0.50	0.50	0.50	24.00	24.00	24.00	24.00	24.00	24.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	9.83
Dispatch	24.00
Data deps.	16.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

99% of peak load performance is reached (96.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 495dbf

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	Latency	Recip. throughput
VMOVUPD (%R15),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD (%R15),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD (%R15),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
ADD $0x100,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
VMOVUPD 0x140(%R15),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0xc0(%R15),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0xc0(%R15),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
ADD $0x300,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
VMOVUPD -0x180(%R15),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD -0x2c0(%R15),%ZMM14,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VPERMT2PD -0x2c0(%R15),%ZMM5,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VPERMT2PD -0x2c0(%R15),%ZMM7,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VPERMT2PD -0x280(%R15),%ZMM8,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VFMADD132PD -0x100(%RSI),%ZMM15,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x200(%R15),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD -0x280(%R15),%ZMM4,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VFMADD132PD -0x100(%RSI),%ZMM0,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x240(%R15),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD -0x280(%R15),%ZMM6,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VFMADD231PD -0x100(%RSI),%ZMM11,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x180(%R15),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM15,%ZMM14,%ZMM13	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM15,%ZMM7,%ZMM1	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM15,%ZMM5,%ZMM0	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD -0x100(%R15),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM12,%ZMM6,%ZMM1	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0xc0(%RSI),%ZMM2,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VPERMT2PD %ZMM12,%ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0xc0(%RSI),%ZMM3,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x140(%R15),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD -0x180(%R15),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM12,%ZMM8,%ZMM13	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0xc0(%RSI),%ZMM9,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x40(%R15),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM3,%ZMM7,%ZMM11	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM3,%ZMM14,%ZMM10	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM3,%ZMM5,%ZMM2	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM15,%ZMM6,%ZMM11	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM15,%ZMM8,%ZMM10	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVAPD %ZMM11,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD -0x80(%RSI),%ZMM13,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VFMADD132PD -0x80(%RSI),%ZMM1,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x80(%R15),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD -0xc0(%R15),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM15,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD -0xc0(%R15),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD132PD -0x80(%RSI),%ZMM0,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0xc0(%R15),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM13,%ZMM7,%ZMM1	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM13,%ZMM14,%ZMM15	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM12,%ZMM6,%ZMM1	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM13,%ZMM5,%ZMM0	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM12,%ZMM8,%ZMM15	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM12,%ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0x40(%RSI),%ZMM2,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VFMADD132PD -0x40(%RSI),%ZMM10,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVAPD %ZMM1,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD -0x40(%RSI),%ZMM9,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
CMP %RSI,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JNE 495dbf <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x42f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi
Source file and lines	inner_product.hpp:155-155
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck)
reading data from caches/RAM (load units are a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 24.00 to 9.83 cycles (2.44x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions
Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 96 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

96: addition or subtraction (all inside FMA instructions)
96: multiply (all inside FMA instructions)

The binary loop is loading 2304 bytes (288 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	60
nb uops	59
loop length	392
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.83 cycles
front end	9.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	12.00	12.00	12.00	12.00	24.00	24.00	0.00	0.00	0.00
cycles	0.75	0.75	0.50	0.50	0.50	24.00	24.00	24.00	24.00	24.00	24.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	9.83
Dispatch	24.00
Data deps.	16.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

99% of peak load performance is reached (96.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 495dbf

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	Latency	Recip. throughput
VMOVUPD (%R15),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD (%R15),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD (%R15),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
ADD $0x100,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
VMOVUPD 0x140(%R15),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0xc0(%R15),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0xc0(%R15),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
ADD $0x300,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
VMOVUPD -0x180(%R15),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD -0x2c0(%R15),%ZMM14,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VPERMT2PD -0x2c0(%R15),%ZMM5,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VPERMT2PD -0x2c0(%R15),%ZMM7,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VPERMT2PD -0x280(%R15),%ZMM8,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VFMADD132PD -0x100(%RSI),%ZMM15,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x200(%R15),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD -0x280(%R15),%ZMM4,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VFMADD132PD -0x100(%RSI),%ZMM0,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x240(%R15),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD -0x280(%R15),%ZMM6,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	1	1	5	1
VFMADD231PD -0x100(%RSI),%ZMM11,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x180(%R15),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM15,%ZMM14,%ZMM13	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM15,%ZMM7,%ZMM1	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM15,%ZMM5,%ZMM0	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD -0x100(%R15),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM12,%ZMM6,%ZMM1	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0xc0(%RSI),%ZMM2,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VPERMT2PD %ZMM12,%ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0xc0(%RSI),%ZMM3,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x140(%R15),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD -0x180(%R15),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM12,%ZMM8,%ZMM13	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0xc0(%RSI),%ZMM9,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x40(%R15),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM3,%ZMM7,%ZMM11	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM3,%ZMM14,%ZMM10	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM3,%ZMM5,%ZMM2	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM15,%ZMM6,%ZMM11	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM15,%ZMM8,%ZMM10	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVAPD %ZMM11,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD -0x80(%RSI),%ZMM13,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VFMADD132PD -0x80(%RSI),%ZMM1,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0x80(%R15),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD -0xc0(%R15),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM15,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD -0xc0(%R15),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD132PD -0x80(%RSI),%ZMM0,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVUPD -0xc0(%R15),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM13,%ZMM7,%ZMM1	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM13,%ZMM14,%ZMM15	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM12,%ZMM6,%ZMM1	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM13,%ZMM5,%ZMM0	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM12,%ZMM8,%ZMM15	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM12,%ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD132PD -0x40(%RSI),%ZMM2,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VFMADD132PD -0x40(%RSI),%ZMM10,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
VMOVAPD %ZMM1,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD -0x40(%RSI),%ZMM9,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	4	1
CMP %RSI,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JNE 495dbf <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x42f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.57	0.07	0.3	0.13	0.13	0.18	0.05	0.2	0.01	0.22	0	0.24	0	0.19

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.07	0.13
2x2	4	0.57	0.86	1.5	0.09	0.16
2x4	8	0.3	0.67	2.25	0.11	0.19
2x8	16	0.13	0.5	4	0.17	0.2
2x16	32	0.05	0.38	8.25	0.22	0.21
2x32	64	0.01	0.18	16.5	0.44	0.22
2x64	128	0	0.08	32.5	0.84	0.24
2x96	192	0	0.08	48.5	0.85	0.19

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency