OV - - Loop 981

0x493f98 VMOVUPD	(%RDI,%RSI,1),%ZMM11    [2]

0x493f9f VMOVUPD	0x40(%RDI,%RSI,1),%ZMM12    [2]

0x493fa7 VMOVUPD	0x80(%RDI,%RSI,1),%ZMM13    [2]

0x493faf VFMADD231PD	(%RDX,%RSI,1),%ZMM11,%ZMM4    [1]

0x493fb6 VMOVUPD	0xc0(%RDI,%RSI,1),%ZMM14    [2]

0x493fbe VMOVUPD	0x100(%RDI,%RSI,1),%ZMM15    [2]

0x493fc6 VMOVUPD	0x140(%RDI,%RSI,1),%ZMM0    [2]

0x493fce VFMADD231PD	0x40(%RDX,%RSI,1),%ZMM12,%ZMM4    [1]

0x493fd6 VMOVUPD	0x180(%RDI,%RSI,1),%ZMM1    [2]

0x493fde VMOVUPD	0x1c0(%RDI,%RSI,1),%ZMM2    [2]

0x493fe6 VFMADD231PD	0x80(%RDX,%RSI,1),%ZMM13,%ZMM4    [1]

0x493fee VFMADD231PD	0xc0(%RDX,%RSI,1),%ZMM14,%ZMM4    [1]

0x493ff6 VFMADD231PD	0x100(%RDX,%RSI,1),%ZMM15,%ZMM4    [1]

0x493ffe VFMADD231PD	0x140(%RDX,%RSI,1),%ZMM0,%ZMM4    [1]

0x494006 VFMADD231PD	0x180(%RDX,%RSI,1),%ZMM1,%ZMM4    [1]

0x49400e VFMADD231PD	0x1c0(%RDX,%RSI,1),%ZMM2,%ZMM4    [1]

0x494016 ADD	$0x200,%RSI

0x49401d CMP	%R12,%RSI

0x494020 JNE	493f98

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 82 - 83

--------------------------------------------------------------------------------

82:   for (int i = 0; i < n; i++)

83:     res += a[i] * b[i];

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.00
Bottlenecks
Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE
Source	inner_product.hpp:82-83
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	32.00
CQA cycles if fully vectorized	32.00
Front-end cycles	3.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	10.67
P5 cycles	10.67
P6 cycles	10.67
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	18.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	4.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.00
Bottlenecks
Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE
Source	inner_product.hpp:82-83
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	32.00
CQA cycles if fully vectorized	32.00
Front-end cycles	3.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	10.67
P5 cycles	10.67
P6 cycles	10.67
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	18.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	4.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE
Source file and lines	inner_product.hpp:82-83
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 64 FMA (fused multiply-add) operations.

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

64: addition or subtraction (all inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary loop is loading 1024 bytes (128 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	19
nb uops	18
loop length	142
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	9
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	5.33	5.33	5.33	4.00	4.00	0.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.50	10.67	10.67	10.67	8.00	8.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Cycles summary

Front-end	3.00
Dispatch	10.67
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

33% of peak load performance is reached (32.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 493f98

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	Latency	Recip. throughput
VMOVUPD (%RDI,%RSI,1),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD 0x40(%RDI,%RSI,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD 0x80(%RDI,%RSI,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VFMADD231PD (%RDX,%RSI,1),%ZMM11,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
VMOVUPD 0xc0(%RDI,%RSI,1),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD 0x100(%RDI,%RSI,1),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD 0x140(%RDI,%RSI,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VFMADD231PD 0x40(%RDX,%RSI,1),%ZMM12,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
VMOVUPD 0x180(%RDI,%RSI,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD 0x1c0(%RDI,%RSI,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VFMADD231PD 0x80(%RDX,%RSI,1),%ZMM13,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
VFMADD231PD 0xc0(%RDX,%RSI,1),%ZMM14,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
VFMADD231PD 0x100(%RDX,%RSI,1),%ZMM15,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
VFMADD231PD 0x140(%RDX,%RSI,1),%ZMM0,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
VFMADD231PD 0x180(%RDX,%RSI,1),%ZMM1,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
VFMADD231PD 0x1c0(%RDX,%RSI,1),%ZMM2,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
ADD $0x200,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP %R12,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 493f98 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE
Source file and lines	inner_product.hpp:82-83
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 64 FMA (fused multiply-add) operations.

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

64: addition or subtraction (all inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary loop is loading 1024 bytes (128 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	19
nb uops	18
loop length	142
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	9
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	5.33	5.33	5.33	4.00	4.00	0.00	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.50	10.67	10.67	10.67	8.00	8.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Cycles summary

Front-end	3.00
Dispatch	10.67
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

33% of peak load performance is reached (32.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 493f98

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	Latency	Recip. throughput
VMOVUPD (%RDI,%RSI,1),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD 0x40(%RDI,%RSI,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD 0x80(%RDI,%RSI,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VFMADD231PD (%RDX,%RSI,1),%ZMM11,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
VMOVUPD 0xc0(%RDI,%RSI,1),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD 0x100(%RDI,%RSI,1),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD 0x140(%RDI,%RSI,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VFMADD231PD 0x40(%RDX,%RSI,1),%ZMM12,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
VMOVUPD 0x180(%RDI,%RSI,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VMOVUPD 0x1c0(%RDI,%RSI,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	1
VFMADD231PD 0x80(%RDX,%RSI,1),%ZMM13,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
VFMADD231PD 0xc0(%RDX,%RSI,1),%ZMM14,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
VFMADD231PD 0x100(%RDX,%RSI,1),%ZMM15,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
VFMADD231PD 0x140(%RDX,%RSI,1),%ZMM0,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
VFMADD231PD 0x180(%RDX,%RSI,1),%ZMM1,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
VFMADD231PD 0x1c0(%RDX,%RSI,1),%ZMM2,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
ADD $0x200,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP %R12,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 493f98 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.67	0.01	0.44	0.02	0.25	0.02	0.12	0.03	0.03	0.02	0.01	0.03	0	0.03

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.02	0.04
2x2	4	0.67	1	1.5	0.02	0.04
2x4	8	0.44	1	2.25	0.03	0.04
2x8	16	0.25	1	4	0.02	0.03
2x16	32	0.12	1	8.25	0.04	0.03
2x32	64	0.03	0.5	16.5	0.06	0.02
2x64	128	0.01	0.25	32.5	0.13	0.03
2x96	192	0	0.18	48.5	0.2	0.03

Report Configuration

Vectorization

Details

Execution units bottlenecks

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency