OV - - Loop 894

	Loop Id: 894	Module: exec	Source: MultiBsplineRef.hpp:276-286	Coverage: 1.21%

0x482334 LEA	0x8(%RDI),%R10

0x482338 VMULSD	(%R11,%RDI,1),%XMM10,%XMM2    [15]

0x48233e VMULSD	(%R12,%RDI,1),%XMM8,%XMM5    [5]

0x482344 VMOVSD	%XMM2,(%R11,%RDI,1)    [15]

0x48234a VMOVSD	%XMM5,(%R12,%RDI,1)    [5]

0x482350 VMULSD	(%RCX,%RDI,1),%XMM11,%XMM3    [2]

0x482355 VMULSD	(%R8,%RDI,1),%XMM7,%XMM0    [8]

0x48235b VMOVSD	%XMM3,(%RCX,%RDI,1)    [2]

0x482360 VMOVSD	%XMM0,(%R8,%RDI,1)    [8]

0x482366 VMULSD	(%RBX,%RDI,1),%XMM12,%XMM9    [7]

0x48236b VMULSD	(%RAX,%RDI,1),%XMM6,%XMM1    [17]

0x482370 VMOVSD	%XMM9,(%RBX,%RDI,1)    [7]

0x482375 VMOVSD	%XMM1,(%RAX,%RDI,1)    [17]

0x48237a VMULSD	(%R15,%RDI,1),%XMM13,%XMM4    [6]

0x482380 VMULSD	0x8(%R12,%RDI,1),%XMM8,%XMM1    [5]

0x482387 VMOVSD	%XMM4,(%R15,%RDI,1)    [6]

0x48238d VMULSD	(%R14,%RDI,1),%XMM14,%XMM5    [10]

0x482393 VMOVSD	%XMM5,(%R14,%RDI,1)    [10]

0x482399 VMULSD	(%R13,%RDI,1),%XMM15,%XMM0    [13]

0x4823a0 VMOVSD	%XMM0,(%R13,%RDI,1)    [13]

0x4823a7 ADD	$0x10,%RDI

0x4823ab VMOVSD	%XMM1,(%R12,%R10,1)    [16]

0x4823b1 VMULSD	(%R11,%R10,1),%XMM10,%XMM9    [14]

0x4823b7 VMULSD	(%R8,%R10,1),%XMM7,%XMM2    [4]

0x4823bd VMOVSD	%XMM9,(%R11,%R10,1)    [14]

0x4823c3 VMOVSD	%XMM2,(%R8,%R10,1)    [4]

0x4823c9 VMULSD	(%RCX,%R10,1),%XMM11,%XMM4    [18]

0x4823cf VMULSD	(%RAX,%R10,1),%XMM6,%XMM3    [9]

0x4823d5 VMOVSD	%XMM4,(%RCX,%R10,1)    [18]

0x4823db VMOVSD	%XMM3,(%RAX,%R10,1)    [9]

0x4823e1 VMULSD	(%RBX,%R10,1),%XMM12,%XMM5    [11]

0x4823e7 VMOVSD	%XMM5,(%RBX,%R10,1)    [11]

0x4823ed VMULSD	(%R15,%R10,1),%XMM13,%XMM0    [3]

0x4823f3 VMOVSD	%XMM0,(%R15,%R10,1)    [3]

0x4823f9 VMULSD	(%R14,%R10,1),%XMM14,%XMM1    [12]

0x4823ff VMOVSD	%XMM1,(%R14,%R10,1)    [12]

0x482405 VMULSD	(%R13,%R10,1),%XMM15,%XMM2    [1]

0x48240c VMOVSD	%XMM2,(%R13,%R10,1)    [1]

0x482413 CMP	%RDI,%R9

0x482416 JNE	482334

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 276 - 286

--------------------------------------------------------------------------------

276:   for (int n = 0; n < num_splines; n++)

277:   {

278:     gx[n] *= dxInv;

279:     gy[n] *= dyInv;

280:     gz[n] *= dzInv;

281:     hxx[n] *= dxx;

282:     hyy[n] *= dyy;

283:     hzz[n] *= dzz;

284:     hxy[n] *= dxy;

285:     hxz[n] *= dxz;

286:     hyz[n] *= dyz;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m
Source	MultiBsplineRef.hpp:276-286
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	2.25
Front-end cycles	6.50
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	12.00
P5 cycles	12.00
P6 cycles	12.00
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	9.00
P12 cycles	9.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	39.00
Nb loads	18.00
Nb stores	18.00
Nb stack references	0.00
FLOP/cycle	1.50
Nb FLOP add-sub	0.00
Nb FLOP mul	18.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	144.00
Stride 0	0.00
Stride 1	0.00
Stride n	17.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m
Source	MultiBsplineRef.hpp:276-286
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	2.25
Front-end cycles	6.50
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	12.00
P5 cycles	12.00
P6 cycles	12.00
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	9.00
P12 cycles	9.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	39.00
Nb loads	18.00
Nb stores	18.00
Nb stack references	0.00
FLOP/cycle	1.50
Nb FLOP add-sub	0.00
Nb FLOP mul	18.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	144.00
Stride 0	0.00
Stride 1	0.00
Stride n	17.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m
Source file and lines	MultiBsplineRef.hpp:276-286
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:276-286.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 12.00 to 2.25 cycles (5.33x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.00 cycles (1.33x speedup).

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Constant non-unit stride: 17 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

18 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 18 FP arithmetical operations:

18: multiply

The binary loop is loading 144 bytes (18 double precision FP elements). The binary loop is storing 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	40
nb uops	39
loop length	232
used x86 registers	12
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	12.00	12.00	12.00	9.00	9.00	0.00	0.00	9.00	9.00
cycles	0.75	0.75	0.50	0.50	0.50	12.00	12.00	12.00	9.00	9.00	0.00	0.00	9.00	9.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.50
Dispatch	12.00
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (12.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 482334

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
LEA 0x8(%RDI),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMULSD (%R11,%RDI,1),%XMM10,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMULSD (%R12,%RDI,1),%XMM8,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM2,(%R11,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD %XMM5,(%R12,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%RCX,%RDI,1),%XMM11,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMULSD (%R8,%RDI,1),%XMM7,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM3,(%RCX,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD %XMM0,(%R8,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%RBX,%RDI,1),%XMM12,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMULSD (%RAX,%RDI,1),%XMM6,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM9,(%RBX,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD %XMM1,(%RAX,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%R15,%RDI,1),%XMM13,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMULSD 0x8(%R12,%RDI,1),%XMM8,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM4,(%R15,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%R14,%RDI,1),%XMM14,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM5,(%R14,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%R13,%RDI,1),%XMM15,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM0,(%R13,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
ADD $0x10,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM1,(%R12,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%R11,%R10,1),%XMM10,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMULSD (%R8,%R10,1),%XMM7,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM9,(%R11,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD %XMM2,(%R8,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%RCX,%R10,1),%XMM11,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMULSD (%RAX,%R10,1),%XMM6,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM4,(%RCX,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD %XMM3,(%RAX,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%RBX,%R10,1),%XMM12,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM5,(%RBX,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%R15,%R10,1),%XMM13,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM0,(%R15,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%R14,%R10,1),%XMM14,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM1,(%R14,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%R13,%R10,1),%XMM15,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM2,(%R13,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %RDI,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 482334 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xa24>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m
Source file and lines	MultiBsplineRef.hpp:276-286
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 12.00 to 2.25 cycles (5.33x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.00 cycles (1.33x speedup).

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Constant non-unit stride: 17 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

18 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 18 FP arithmetical operations:

18: multiply

The binary loop is loading 144 bytes (18 double precision FP elements). The binary loop is storing 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	40
nb uops	39
loop length	232
used x86 registers	12
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	12.00	12.00	12.00	9.00	9.00	0.00	0.00	9.00	9.00
cycles	0.75	0.75	0.50	0.50	0.50	12.00	12.00	12.00	9.00	9.00	0.00	0.00	9.00	9.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.50
Dispatch	12.00
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (12.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 482334

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
LEA 0x8(%RDI),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMULSD (%R11,%RDI,1),%XMM10,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMULSD (%R12,%RDI,1),%XMM8,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM2,(%R11,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD %XMM5,(%R12,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%RCX,%RDI,1),%XMM11,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMULSD (%R8,%RDI,1),%XMM7,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM3,(%RCX,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD %XMM0,(%R8,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%RBX,%RDI,1),%XMM12,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMULSD (%RAX,%RDI,1),%XMM6,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM9,(%RBX,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD %XMM1,(%RAX,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%R15,%RDI,1),%XMM13,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMULSD 0x8(%R12,%RDI,1),%XMM8,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM4,(%R15,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%R14,%RDI,1),%XMM14,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM5,(%R14,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%R13,%RDI,1),%XMM15,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM0,(%R13,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
ADD $0x10,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM1,(%R12,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%R11,%R10,1),%XMM10,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMULSD (%R8,%R10,1),%XMM7,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM9,(%R11,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD %XMM2,(%R8,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%RCX,%R10,1),%XMM11,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMULSD (%RAX,%R10,1),%XMM6,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM4,(%RCX,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD %XMM3,(%RAX,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%RBX,%R10,1),%XMM12,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM5,(%RBX,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%R15,%R10,1),%XMM13,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM0,(%R15,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%R14,%R10,1),%XMM14,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM1,(%R14,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD (%R13,%R10,1),%XMM15,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM2,(%R13,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %RDI,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 482334 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0xa24>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.71	0.34	0.45	0.63	0.25	0.68	0.13	0.58	0.06	0.31	0.02	0.25	0.01	0.23

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.7	1.21
2x2	4	0.71	1.06	1.5	0.7	1.15
2x4	8	0.45	1.02	2.25	0.71	1.16
2x8	16	0.25	1.02	4	0.74	0.91
2x16	32	0.13	1.1	8.25	0.74	0.67
2x32	64	0.06	1.06	16.5	0.75	0.33
2x64	128	0.02	0.71	32.5	1.05	0.26
2x96	192	0.01	0.6	48.5	1.03	0.23

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency