OV - - Loop 586

0x45432c VADDPD	(%R9),%ZMM4,%ZMM1    [1]

0x454332 ADD	$0x200,%R9

0x454339 VADDPD	-0x1c0(%R9),%ZMM1,%ZMM2    [2]

0x454340 VADDPD	-0x180(%R9),%ZMM2,%ZMM3    [2]

0x454347 VADDPD	-0x140(%R9),%ZMM3,%ZMM5    [2]

0x45434e VADDPD	-0x100(%R9),%ZMM5,%ZMM6    [2]

0x454355 VADDPD	-0xc0(%R9),%ZMM6,%ZMM7    [2]

0x45435c VADDPD	-0x80(%R9),%ZMM7,%ZMM8    [2]

0x454363 VADDPD	-0x40(%R9),%ZMM8,%ZMM4    [2]

0x45436a CMP	%R15,%R9

0x45436d JNE	45432c

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_numeric.h: 140 - 141

--------------------------------------------------------------------------------

140:       for (; __first != __last; ++__first)

141: 	__init = _GLIBCXX_MOVE_IF_20(__init) + *__first;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.00
Bottlenecks
Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE
Source	stl_numeric.h:140-141
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	24.00
Front-end cycles	1.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	5.33
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	24
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	10.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.67
Nb FLOP add-sub	64.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.00
Bottlenecks
Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE
Source	stl_numeric.h:140-141
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	24.00
Front-end cycles	1.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	5.33
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	24
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	10.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.67
Nb FLOP add-sub	64.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE
Source file and lines	stl_numeric.h:140-141
Module	exec

The loop is defined in /cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_numeric.h:140-141.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

64: addition or subtraction

The binary loop is loading 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	11
nb uops	10
loop length	67
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	8
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.67 cycles
front end	1.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	2.67	2.67	2.67	0.00	0.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.50	5.33	5.33	5.33	0.00	0.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	24.00

Cycles summary

Front-end	1.67
Dispatch	8.00
Data deps.	24.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45432c

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	Latency	Recip. throughput
VADDPD (%R9),%ZMM4,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	1
ADD $0x200,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VADDPD -0x1c0(%R9),%ZMM1,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	1
VADDPD -0x180(%R9),%ZMM2,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	1
VADDPD -0x140(%R9),%ZMM3,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	1
VADDPD -0x100(%R9),%ZMM5,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	1
VADDPD -0xc0(%R9),%ZMM6,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	1
VADDPD -0x80(%R9),%ZMM7,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	1
VADDPD -0x40(%R9),%ZMM8,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	1
CMP %R15,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 45432c <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x14c>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE
Source file and lines	stl_numeric.h:140-141
Module	exec

The loop is defined in /cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_numeric.h:140-141.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

64: addition or subtraction

The binary loop is loading 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	11
nb uops	10
loop length	67
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	8
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.67 cycles
front end	1.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	2.67	2.67	2.67	0.00	0.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.50	5.33	5.33	5.33	0.00	0.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	24.00

Cycles summary

Front-end	1.67
Dispatch	8.00
Data deps.	24.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 45432c

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	Latency	Recip. throughput
VADDPD (%R9),%ZMM4,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	1
ADD $0x200,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VADDPD -0x1c0(%R9),%ZMM1,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	1
VADDPD -0x180(%R9),%ZMM2,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	1
VADDPD -0x140(%R9),%ZMM3,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	1
VADDPD -0x100(%R9),%ZMM5,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	1
VADDPD -0xc0(%R9),%ZMM6,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	1
VADDPD -0x80(%R9),%ZMM7,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	1
VADDPD -0x40(%R9),%ZMM8,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	1
CMP %R15,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 45432c <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x14c>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.67	0.02	0.44	0.02	0.25	0.03	0.12	0.03	0.04	0.02	0.02	0.01	0.01	0.01

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.02	0.04
2x2	4	0.67	1	1.5	0.04	0.05
2x4	8	0.44	1	2.25	0.02	0.03
2x8	16	0.25	1	4	0.04	0.04
2x16	32	0.12	1	8.25	0.03	0.03
2x32	64	0.04	0.67	16.5	0.04	0.02
2x64	128	0.02	0.67	32.5	0.07	0.01
2x96	192	0.01	0.67	48.5	0.07	0.01

Report Configuration

Vectorization

Details

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency