OV - - Loop 582

	Loop Id: 582	Module: exec	Source: TwoBodyJastrowRef.h:342-347	Coverage: 0.28%

0x4539b5 VMOVUPD	(%RBX,%R12,1),%ZMM13    [4]

0x4539bc VMOVUPD	(%RAX,%R12,1),%ZMM4    [3]

0x4539c3 VMOVUPD	(%RCX,%R12,1),%ZMM8    [5]

0x4539ca VMOVUPD	(%RSI,%R12,1),%ZMM1    [2]

0x4539d1 VFMADD132PD	(%R9,%R12,1),%ZMM1,%ZMM8    [1]

0x4539d8 VMOVUPD	0x40(%RSI,%R12,1),%ZMM5    [2]

0x4539e0 VFNMADD231PD	%ZMM13,%ZMM4,%ZMM8

0x4539e6 VFMADD231PD	%ZMM13,%ZMM4,%ZMM2

0x4539ec VMOVUPD	%ZMM8,(%RSI,%R12,1)    [2]

0x4539f3 VMOVUPD	0x40(%RBX,%R12,1),%ZMM13    [4]

0x4539fb VMOVUPD	0x40(%RAX,%R12,1),%ZMM4    [3]

0x453a03 VMOVUPD	0x40(%RCX,%R12,1),%ZMM12    [5]

0x453a0b VFMADD132PD	0x40(%R9,%R12,1),%ZMM5,%ZMM12    [1]

0x453a13 VMOVUPD	0xc0(%RSI,%R12,1),%ZMM5    [2]

0x453a1b VFNMADD231PD	%ZMM13,%ZMM4,%ZMM12

0x453a21 VFMADD132PD	%ZMM13,%ZMM2,%ZMM4

0x453a27 VMOVUPD	0x80(%RSI,%R12,1),%ZMM13    [2]

0x453a2f VMOVUPD	%ZMM12,0x40(%RSI,%R12,1)    [2]

0x453a37 VMOVUPD	0x80(%RBX,%R12,1),%ZMM8    [4]

0x453a3f VMOVUPD	0x80(%RAX,%R12,1),%ZMM2    [3]

0x453a47 VMOVUPD	0x80(%RCX,%R12,1),%ZMM1    [5]

0x453a4f VFMADD132PD	0x80(%R9,%R12,1),%ZMM13,%ZMM1    [1]

0x453a57 VFNMADD231PD	%ZMM8,%ZMM2,%ZMM1

0x453a5d VFMADD132PD	%ZMM8,%ZMM4,%ZMM2

0x453a63 VMOVUPD	%ZMM1,0x80(%RSI,%R12,1)    [2]

0x453a6b VMOVUPD	0xc0(%RBX,%R12,1),%ZMM12    [4]

0x453a73 VMOVUPD	0xc0(%RAX,%R12,1),%ZMM8    [3]

0x453a7b VMOVUPD	0xc0(%RCX,%R12,1),%ZMM4    [5]

0x453a83 VFMADD132PD	0xc0(%R9,%R12,1),%ZMM5,%ZMM4    [1]

0x453a8b VFNMADD231PD	%ZMM12,%ZMM8,%ZMM4

0x453a91 VFMADD231PD	%ZMM12,%ZMM8,%ZMM2

0x453a97 VMOVUPD	%ZMM4,0xc0(%RSI,%R12,1)    [2]

0x453a9f ADD	$0x100,%R12

0x453aa6 CMP	%R12,-0x88(%RBP)    [6]

0x453aad JNE	4539b5

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 342 - 347

--------------------------------------------------------------------------------

342:     for (int jat = 0; jat < N; jat++)

343:     {

344:       const valT newg = cur_du_pt[jat] * new_dX[jat];

345:       const valT dg   = newg - old_du_pt[jat] * old_dX[jat];

346:       save_g[jat] -= dg;

347:       cur_g += newg;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks
Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi
Source	TwoBodyJastrowRef.h:342-347
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	16.00
Front-end cycles	6.33
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	15.00
P5 cycles	15.00
P6 cycles	15.00
P7 cycles	12.00
P8 cycles	12.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	38.00
Nb loads	21.00
Nb stores	4.00
Nb stack references	1.00
FLOP/cycle	12.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	96.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	96.50
Bytes prefetched	0.00
Bytes loaded	1288.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks
Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi
Source	TwoBodyJastrowRef.h:342-347
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	16.00
Front-end cycles	6.33
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	15.00
P5 cycles	15.00
P6 cycles	15.00
P7 cycles	12.00
P8 cycles	12.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	38.00
Nb loads	21.00
Nb stores	4.00
Nb stack references	1.00
FLOP/cycle	12.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	96.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	96.50
Bytes prefetched	0.00
Bytes loaded	1288.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi
Source file and lines	TwoBodyJastrowRef.h:342-347
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:342-347.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 96 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 4 occurrences

Type of elements and instruction set

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

96: addition or subtraction (all inside FMA instructions)
96: multiply (all inside FMA instructions)

The binary loop is loading 1288 bytes (161 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	35
nb uops	38
loop length	254
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	7
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.33 cycles
front end	6.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	8.33	8.33	8.33	6.00	6.00	0.00	0.00	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	15.00	15.00	15.00	12.00	12.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	6.33
Dispatch	15.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

83% of peak load performance is reached (80.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (16.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4539b5

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%RBX,%R12,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD (%RAX,%R12,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD (%RCX,%R12,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD (%RSI,%R12,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFMADD132PD (%R9,%R12,1),%ZMM1,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD 0x40(%RSI,%R12,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD231PD %ZMM13,%ZMM4,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VFMADD231PD %ZMM13,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VMOVUPD %ZMM8,(%RSI,%R12,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x40(%RBX,%R12,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x40(%RAX,%R12,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x40(%RCX,%R12,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFMADD132PD 0x40(%R9,%R12,1),%ZMM5,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD 0xc0(%RSI,%R12,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD231PD %ZMM13,%ZMM4,%ZMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VFMADD132PD %ZMM13,%ZMM2,%ZMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VMOVUPD 0x80(%RSI,%R12,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM12,0x40(%RSI,%R12,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x80(%RBX,%R12,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x80(%RAX,%R12,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x80(%RCX,%R12,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFMADD132PD 0x80(%R9,%R12,1),%ZMM13,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VFNMADD231PD %ZMM8,%ZMM2,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VFMADD132PD %ZMM8,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VMOVUPD %ZMM1,0x80(%RSI,%R12,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0xc0(%RBX,%R12,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0xc0(%RAX,%R12,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0xc0(%RCX,%R12,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFMADD132PD 0xc0(%R9,%R12,1),%ZMM5,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VFNMADD231PD %ZMM12,%ZMM8,%ZMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VFMADD231PD %ZMM12,%ZMM8,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VMOVUPD %ZMM4,0xc0(%RSI,%R12,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R12,-0x88(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
JNE 4539b5 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0x5a5>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi
Source file and lines	TwoBodyJastrowRef.h:342-347
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 96 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 4 occurrences

Type of elements and instruction set

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

96: addition or subtraction (all inside FMA instructions)
96: multiply (all inside FMA instructions)

The binary loop is loading 1288 bytes (161 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	35
nb uops	38
loop length	254
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	7
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.33 cycles
front end	6.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	8.33	8.33	8.33	6.00	6.00	0.00	0.00	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	15.00	15.00	15.00	12.00	12.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	6.33
Dispatch	15.00
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

83% of peak load performance is reached (80.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (16.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4539b5

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%RBX,%R12,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD (%RAX,%R12,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD (%RCX,%R12,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD (%RSI,%R12,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFMADD132PD (%R9,%R12,1),%ZMM1,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD 0x40(%RSI,%R12,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD231PD %ZMM13,%ZMM4,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VFMADD231PD %ZMM13,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VMOVUPD %ZMM8,(%RSI,%R12,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x40(%RBX,%R12,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x40(%RAX,%R12,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x40(%RCX,%R12,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFMADD132PD 0x40(%R9,%R12,1),%ZMM5,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD 0xc0(%RSI,%R12,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD231PD %ZMM13,%ZMM4,%ZMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VFMADD132PD %ZMM13,%ZMM2,%ZMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VMOVUPD 0x80(%RSI,%R12,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM12,0x40(%RSI,%R12,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x80(%RBX,%R12,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x80(%RAX,%R12,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x80(%RCX,%R12,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFMADD132PD 0x80(%R9,%R12,1),%ZMM13,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VFNMADD231PD %ZMM8,%ZMM2,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VFMADD132PD %ZMM8,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VMOVUPD %ZMM1,0x80(%RSI,%R12,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0xc0(%RBX,%R12,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0xc0(%RAX,%R12,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0xc0(%RCX,%R12,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFMADD132PD 0xc0(%R9,%R12,1),%ZMM5,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VFNMADD231PD %ZMM12,%ZMM8,%ZMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VFMADD231PD %ZMM12,%ZMM8,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	1
VMOVUPD %ZMM4,0xc0(%RSI,%R12,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R12,-0x88(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
JNE 4539b5 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0x5a5>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.57	0.13	0.36	0.2	0.15	0.28	0.07	0.27	0.02	0.3	0	0.39	0	0.35

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.13	0.28
2x2	4	0.57	0.86	1.5	0.15	0.31
2x4	8	0.36	0.8	2.25	0.2	0.31
2x8	16	0.15	0.6	4	0.22	0.33
2x16	32	0.07	0.57	8.25	0.27	0.29
2x32	64	0.02	0.26	16.5	0.58	0.3
2x64	128	0	0.1	32.5	1.48	0.39
2x96	192	0	0.09	48.5	1.64	0.35

Report Configuration

Vectorization

Details

Execution units bottlenecks

FMA

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

FMA

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency