OV - - Loop 579

	Loop Id: 579	Module: exec	Source: BsplineFunctor.h:305-336	Coverage: 0.08%

0x4532c0 VMOVSD	(%RSI,%R14,8),%XMM5    [5]

0x4532c6 VMULSD	%XMM5,%XMM1,%XMM21

0x4532cc VRNDSCALESD	$0xb,%XMM21,%XMM21,%XMM12

0x4532d3 VCVTTSD2SI	%XMM21,%EAX

0x4532d9 VSUBSD	%XMM12,%XMM21,%XMM0

0x4532df CLTQ

0x4532e1 VBROADCASTSD	%XMM0,%YMM18

0x4532e7 VMULSD	%XMM0,%XMM0,%XMM22

0x4532ed VMULSD	%XMM22,%XMM0,%XMM12

0x4532f3 VBROADCASTSD	%XMM12,%YMM0

0x4532f8 VMOVAPD	%YMM14,%YMM19

0x4532fe VMOVAPD	%YMM15,%YMM17

0x453304 VMULPD	%YMM3,%YMM0,%YMM12

0x453308 VMOVUPD	(%R11,%RAX,8),%YMM0    [4]

0x45330e VFMADD132PD	%YMM18,%YMM4,%YMM19

0x453314 VBROADCASTSD	%XMM22,%YMM20

0x45331a MOVSXD	(%R8,%R14,4),%R10    [2]

0x45331e VDIVSD	%XMM5,%XMM11,%XMM5

0x453322 INC	%R14

0x453325 VFMADD132PD	%YMM18,%YMM16,%YMM17

0x45332b VFMADD132PD	%YMM8,%YMM7,%YMM18

0x453331 VFMADD231PD	%YMM6,%YMM20,%YMM19

0x453337 VFMADD132PD	%YMM2,%YMM12,%YMM20

0x45333d VMULPD	%YMM0,%YMM18,%YMM12

0x453343 ADD	%RDX,%R10

0x453346 SAL	$0x3,%R10

0x45334a VADDPD	%YMM20,%YMM17,%YMM24

0x453350 VMULPD	%YMM0,%YMM19,%YMM23

0x453356 VEXTRACTF64X2	$0x1,%YMM12,%XMM26

0x45335d VADDPD	%XMM12,%XMM26,%XMM27

0x453363 VMULPD	%YMM0,%YMM24,%YMM25

0x453369 VEXTRACTF64X2	$0x1,%YMM23,%XMM28

0x453370 VADDPD	%XMM23,%XMM28,%XMM29

0x453376 VUNPCKHPD	%XMM27,%XMM27,%XMM0

0x45337c VADDPD	%XMM27,%XMM0,%XMM12

0x453382 VMULSD	%XMM12,%XMM10,%XMM0

0x453387 VUNPCKHPD	%XMM29,%XMM29,%XMM12

0x45338d VMOVSD	%XMM0,(%RCX,%R10,1)    [6]

0x453393 VADDPD	%XMM29,%XMM12,%XMM0

0x453399 VMULSD	%XMM0,%XMM1,%XMM12

0x45339d VMULSD	%XMM12,%XMM5,%XMM0

0x4533a2 VEXTRACTF64X2	$0x1,%YMM25,%XMM5

0x4533a9 VMOVSD	%XMM0,(%R12,%R10,1)    [3]

0x4533af VADDPD	%XMM25,%XMM5,%XMM0

0x4533b5 VUNPCKHPD	%XMM0,%XMM0,%XMM12

0x4533b9 VADDPD	%XMM0,%XMM12,%XMM5

0x4533bd VMOVLPD	%XMM5,(%RBX,%R10,1)    [1]

0x4533c3 CMP	%R15,%R14

0x4533c6 JNE	4532c0

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 305 - 336

--------------------------------------------------------------------------------

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.07
CQA speedup if fully vectorized	1.60
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P8,
Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b
Source	BsplineFunctor.h:305-336
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	8.38
CQA cycles if fully vectorized	5.63
Front-end cycles	8.00
DIV/SQRT cycles	1.25
P0 cycles	1.25
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	0.50
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	9.00
P8 cycles	8.75
P9 cycles	8.58
P10 cycles	8.67
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	5.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	48.00
Nb loads	3.00
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	8.89
Nb FLOP add-sub	17.00
Nb FLOP mul	22.00
Nb FLOP fma	20.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.56
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	24.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	0.00
Vectorization ratio all	51.16
Vectorization ratio load	50.00
Vectorization ratio store	0.00
Vectorization ratio mul	40.00
Vectorization ratio add_sub	87.50
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	35.71
Vector-efficiency ratio all	26.45
Vector-efficiency ratio load	31.25
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	27.50
Vector-efficiency ratio add_sub	26.56
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	20.54

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.07
CQA speedup if fully vectorized	1.60
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P8,
Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b
Source	BsplineFunctor.h:305-336
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	8.38
CQA cycles if fully vectorized	5.63
Front-end cycles	8.00
DIV/SQRT cycles	1.25
P0 cycles	1.25
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	0.50
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	9.00
P8 cycles	8.75
P9 cycles	8.58
P10 cycles	8.67
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	5.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	48.00
Nb loads	3.00
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	8.89
Nb FLOP add-sub	17.00
Nb FLOP mul	22.00
Nb FLOP fma	20.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.56
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	24.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	0.00
Vectorization ratio all	51.16
Vectorization ratio load	50.00
Vectorization ratio store	0.00
Vectorization ratio mul	40.00
Vectorization ratio add_sub	87.50
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	35.71
Vector-efficiency ratio all	26.45
Vector-efficiency ratio load	31.25
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	27.50
Vector-efficiency ratio add_sub	26.56
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	20.54

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b
Source file and lines	BsplineFunctor.h:305-336
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305-336.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 26% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 9.00 to 5.62 cycles (1.60x speedup).

Details

51% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
87% of SSE/AVX addition or subtraction instructions are used in vector version.
40% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
35% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTSD2SI: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 1 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 1 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences
VCVTTSD2SI (FP64 to INT32/64, scalar): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

9 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 10 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 80 FP arithmetical operations:

37: addition or subtraction (20 inside FMA instructions)
42: multiply (20 inside FMA instructions)
1: divide

The binary loop is loading 44 bytes (5 double precision FP elements). The binary loop is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 1.18 FP operations per loaded or stored byte.

General properties

nb instructions	49
nb uops	48
loop length	268
used x86 registers	11
used mmx registers	0
used xmm registers	14
used ymm registers	18
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.80

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.00 cycles
front end	8.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.25	1.25	1.00	1.00	0.50	2.00	2.00	2.00	9.00	8.75	8.58	8.67	2.00	2.00
cycles	1.25	1.25	1.00	1.00	0.50	2.00	2.00	2.00	9.00	8.75	8.58	8.67	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	5.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.00
Dispatch	9.00
DIV/SQRT	5.00
Data deps.	1.00
Overall L1	9.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	52%
load	50%
store	0%
mul	40%
add-sub	87%
fma	100%
div/sqrt	0%
other	38%

INT+FP

all	51%
load	50%
store	0%
mul	40%
add-sub	87%
fma	100%
div/sqrt	0%
other	35%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	26%
load	31%
store	12%
mul	27%
add-sub	26%
fma	50%
div/sqrt	12%
other	21%

INT+FP

all	26%
load	31%
store	12%
mul	27%
add-sub	26%
fma	50%
div/sqrt	12%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

5% of peak load performance is reached (4.89 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.67 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4532c0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVSD (%RSI,%R14,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMULSD %XMM5,%XMM1,%XMM21	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VRNDSCALESD $0xb,%XMM21,%XMM21,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VCVTTSD2SI %XMM21,%EAX	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	8	1
VSUBSD %XMM12,%XMM21,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
CLTQ
VBROADCASTSD %XMM0,%YMM18	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMULSD %XMM0,%XMM0,%XMM22	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM22,%XMM0,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VBROADCASTSD %XMM12,%YMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %YMM14,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD %YMM15,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMULPD %YMM3,%YMM0,%YMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVUPD (%R11,%RAX,8),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VFMADD132PD %YMM18,%YMM4,%YMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VBROADCASTSD %XMM22,%YMM20	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
MOVSXD (%R8,%R14,4),%R10	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
VDIVSD %XMM5,%XMM11,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
INC %R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VFMADD132PD %YMM18,%YMM16,%YMM17	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD132PD %YMM8,%YMM7,%YMM18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM6,%YMM20,%YMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD132PD %YMM2,%YMM12,%YMM20	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMULPD %YMM0,%YMM18,%YMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD %RDX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SAL $0x3,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
VADDPD %YMM20,%YMM17,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULPD %YMM0,%YMM19,%YMM23	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VEXTRACTF64X2 $0x1,%YMM12,%XMM26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VADDPD %XMM12,%XMM26,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULPD %YMM0,%YMM24,%YMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VEXTRACTF64X2 $0x1,%YMM23,%XMM28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VADDPD %XMM23,%XMM28,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKHPD %XMM27,%XMM27,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDPD %XMM27,%XMM0,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM12,%XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VUNPCKHPD %XMM29,%XMM29,%XMM12	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VMOVSD %XMM0,(%RCX,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VADDPD %XMM29,%XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM0,%XMM1,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM12,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VEXTRACTF64X2 $0x1,%YMM25,%XMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVSD %XMM0,(%R12,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VADDPD %XMM25,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKHPD %XMM0,%XMM0,%XMM12	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDPD %XMM0,%XMM12,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVLPD %XMM5,(%RBX,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
CMP %R15,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 4532c0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x540>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b
Source file and lines	BsplineFunctor.h:305-336
Module	exec

gain
potential
hint
expert

Vectorization

Details

51% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
87% of SSE/AVX addition or subtraction instructions are used in vector version.
40% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
35% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTSD2SI: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 1 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 1 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences
VCVTTSD2SI (FP64 to INT32/64, scalar): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 80 FP arithmetical operations:

37: addition or subtraction (20 inside FMA instructions)
42: multiply (20 inside FMA instructions)
1: divide

The binary loop is loading 44 bytes (5 double precision FP elements). The binary loop is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 1.18 FP operations per loaded or stored byte.

General properties

nb instructions	49
nb uops	48
loop length	268
used x86 registers	11
used mmx registers	0
used xmm registers	14
used ymm registers	18
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.80

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.00 cycles
front end	8.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.25	1.25	1.00	1.00	0.50	2.00	2.00	2.00	9.00	8.75	8.58	8.67	2.00	2.00
cycles	1.25	1.25	1.00	1.00	0.50	2.00	2.00	2.00	9.00	8.75	8.58	8.67	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	5.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.00
Dispatch	9.00
DIV/SQRT	5.00
Data deps.	1.00
Overall L1	9.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	52%
load	50%
store	0%
mul	40%
add-sub	87%
fma	100%
div/sqrt	0%
other	38%

INT+FP

all	51%
load	50%
store	0%
mul	40%
add-sub	87%
fma	100%
div/sqrt	0%
other	35%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	26%
load	31%
store	12%
mul	27%
add-sub	26%
fma	50%
div/sqrt	12%
other	21%

INT+FP

all	26%
load	31%
store	12%
mul	27%
add-sub	26%
fma	50%
div/sqrt	12%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

5% of peak load performance is reached (4.89 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.67 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4532c0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVSD (%RSI,%R14,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMULSD %XMM5,%XMM1,%XMM21	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VRNDSCALESD $0xb,%XMM21,%XMM21,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VCVTTSD2SI %XMM21,%EAX	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	8	1
VSUBSD %XMM12,%XMM21,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
CLTQ
VBROADCASTSD %XMM0,%YMM18	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMULSD %XMM0,%XMM0,%XMM22	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM22,%XMM0,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VBROADCASTSD %XMM12,%YMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %YMM14,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD %YMM15,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMULPD %YMM3,%YMM0,%YMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVUPD (%R11,%RAX,8),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VFMADD132PD %YMM18,%YMM4,%YMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VBROADCASTSD %XMM22,%YMM20	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
MOVSXD (%R8,%R14,4),%R10	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
VDIVSD %XMM5,%XMM11,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
INC %R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VFMADD132PD %YMM18,%YMM16,%YMM17	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD132PD %YMM8,%YMM7,%YMM18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM6,%YMM20,%YMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD132PD %YMM2,%YMM12,%YMM20	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMULPD %YMM0,%YMM18,%YMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD %RDX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SAL $0x3,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
VADDPD %YMM20,%YMM17,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULPD %YMM0,%YMM19,%YMM23	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VEXTRACTF64X2 $0x1,%YMM12,%XMM26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VADDPD %XMM12,%XMM26,%XMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULPD %YMM0,%YMM24,%YMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VEXTRACTF64X2 $0x1,%YMM23,%XMM28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VADDPD %XMM23,%XMM28,%XMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKHPD %XMM27,%XMM27,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDPD %XMM27,%XMM0,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM12,%XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VUNPCKHPD %XMM29,%XMM29,%XMM12	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VMOVSD %XMM0,(%RCX,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VADDPD %XMM29,%XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM0,%XMM1,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM12,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VEXTRACTF64X2 $0x1,%YMM25,%XMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVSD %XMM0,(%R12,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VADDPD %XMM25,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKHPD %XMM0,%XMM0,%XMM12	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDPD %XMM0,%XMM12,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVLPD %XMM5,(%RBX,%R10,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
CMP %R15,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 4532c0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x540>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.67	0.02	0.44	0.03	0.19	0.06	0.12	0.04	0.05	0.03	0.01	0.03	0.01	0.03

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.04	0.08
2x2	4	0.67	1	1.5	0.03	0.07
2x4	8	0.44	1	2.25	0.04	0.06
2x8	16	0.19	0.75	4	0.06	0.07
2x16	32	0.12	1	8.25	0.04	0.04
2x32	64	0.05	0.75	16.5	0.05	0.03
2x64	128	0.01	0.38	32.5	0.14	0.03
2x96	192	0.01	0.3	48.5	0.16	0.03

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency