OV - - Function _ZN11qmcplusplus11ParticleSet10acceptMoveEi

	Function: _ZN11qmcplusplus11ParticleSet10acceptMoveEi	Module: exec	Source: ParticleSet.cpp:381-395 [...]	Coverage: 0.01%

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/refwrap.h: 347 - 347

--------------------------------------------------------------------------------

347:       { return *_M_data; }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.cpp: 381 - 395

--------------------------------------------------------------------------------

381: {

[...]

388:   coordinates_->setOneParticlePos(active_pos_, iat);

389:   for (int i = 0; i < DistTables.size(); i++)

390:     DistTables[i]->update(iat);

391:

392:   R[iat]       = active_pos_;

393:   spins[iat]   = active_spin_val_;

394:   active_ptcl_ = -1;

395: }

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h: 990 - 990

--------------------------------------------------------------------------------

990:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/unique_ptr.h: 199 - 199

--------------------------------------------------------------------------------

199:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

0x4bfad0 PUSH	%RBP

0x4bfad1 MOV	%RSP,%RBP

0x4bfad4 PUSH	%R15

0x4bfad6 PUSH	%R14

0x4bfad8 PUSH	%R13

0x4bfada PUSH	%R12

0x4bfadc PUSH	%RBX

0x4bfadd MOV	%RDI,%R12

0x4bfae0 MOVSXD	%ESI,%R14

0x4bfae3 SUB	$0x8,%RSP

0x4bfae7 MOV	0x210(%RDI),%RAX

0x4bfaee MOV	0x10(%RAX),%R15

0x4bfaf2 MOV	%R15,%RDI

0x4bfaf5 CALL	51ed20 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x4bfafa MOV	0x278(%R12),%RDI

0x4bfb02 LEA	0x128(%R12),%RSI

0x4bfb0a MOV	%R14,%RDX

0x4bfb0d MOV	(%RDI),%RCX

0x4bfb10 CALLQ	0x30(%RCX)

0x4bfb13 MOV	0x1e0(%R12),%RSI

0x4bfb1b CMP	%RSI,0x1e8(%R12)

0x4bfb23 JE	4bfb5c

0x4bfb25 MOV	%R14,%R13

0x4bfb28 XOR	%EBX,%EBX

0x4bfb2a NOPW	(%RAX,%RAX,1)

(1251) 0x4bfb30 MOV	(%RSI,%RBX,8),%RDI

(1251) 0x4bfb34 MOV	%R13D,%ESI

(1251) 0x4bfb37 MOV	(%RDI),%RDX

(1251) 0x4bfb3a CALLQ	0x38(%RDX)

(1251) 0x4bfb3d MOV	0x1e0(%R12),%RSI

(1251) 0x4bfb45 MOV	0x1e8(%R12),%RDI

(1251) 0x4bfb4d INC	%RBX

(1251) 0x4bfb50 SUB	%RSI,%RDI

(1251) 0x4bfb53 SAR	$0x3,%RDI

(1251) 0x4bfb57 CMP	%RDI,%RBX

(1251) 0x4bfb5a JB	4bfb30

0x4bfb5c MOV	0x40(%R12),%R9

0x4bfb61 VMOVDQU	0x128(%R12),%XMM1

0x4bfb6b LEA	(%R14,%R14,2),%R8

0x4bfb6f MOV	0x68(%R12),%RAX

0x4bfb74 MOV	%R15,%RDI

0x4bfb77 LEA	(%R9,%R8,8),%R10

0x4bfb7b VMOVDQU	%XMM1,(%R10)

0x4bfb80 MOV	0x138(%R12),%R11

0x4bfb88 MOV	%R11,0x10(%R10)

0x4bfb8c VMOVSD	0x140(%R12),%XMM0

0x4bfb96 VMOVSD	%XMM0,(%RAX,%R14,8)

0x4bfb9c MOVL	$-0x1,0x124(%R12)

0x4bfba8 CALL	51ef50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x4bfbad ADD	$0x8,%RSP

0x4bfbb1 POP	%RBX

0x4bfbb2 POP	%R12

0x4bfbb4 POP	%R13

0x4bfbb6 POP	%R14

0x4bfbb8 POP	%R15

0x4bfbba POP	%RBP

0x4bfbbb RET

0x4bfbbc MOV	%RAX,%R12

0x4bfbbf JMP	40632a

0x4bfbc4 NOPW	%CS:(%RAX,%RAX,1)

0x4bfbcf NOP

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ParticleSet.cpp:381-395
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/refwrap.h:347
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.cpp:381,388-395
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:990
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/unique_ptr.h:199

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.67 to 1.33 cycles (6.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 8.67 to 1.40 cycles (6.21x speedup).

Details

14% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

16% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv: 1 occurrences
_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv: 1 occurrences
unknown: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 104 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	50
nb uops	52
loop length	212
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.00	2.50	2.25	2.25	3.00	6.33	6.33	6.33	0.00	0.00	0.00	0.00	1.00	1.00
cycles	3.00	2.50	2.25	2.25	3.00	6.33	6.33	6.33	0.00	0.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.67
Dispatch	6.33
Overall L1	8.67

Vectorization ratios

INT

all	16%
load	20%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	16%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	13%
load	15%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	13%
load	14%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.67 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.15 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.67 to 6.33 cycles (1.37x speedup).

ASM code

In the binary file, the address of the function is: 4bfad0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVSXD %ESI,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x210(%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x10(%RAX),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 51ed20 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV 0x278(%R12),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA 0x128(%R12),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV (%RDI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CALLQ 0x30(%RCX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	0	0	2.20
MOV 0x1e0(%R12),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CMP %RSI,0x1e8(%R12)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JE 4bfb5c <_ZN11qmcplusplus11ParticleSet10acceptMoveEi+0x8c>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0x40(%R12),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVDQU 0x128(%R12),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
LEA (%R14,%R14,2),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x68(%R12),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%R9,%R8,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVDQU %XMM1,(%R10)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x138(%R12),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R11,0x10(%R10)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVSD 0x140(%R12),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM0,(%RAX,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVL $-0x1,0x124(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CALL 51ef50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
ADD $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 40632a <_ZN11qmcplusplus11ParticleSet10acceptMoveEi.cold>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	ParticleSet.cpp:381-395
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/refwrap.h:347
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.cpp:381,388-395
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:990
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/unique_ptr.h:199

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.67 to 1.33 cycles (6.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

14% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

16% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv: 1 occurrences
_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv: 1 occurrences
unknown: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 104 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	50
nb uops	52
loop length	212
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.00	2.50	2.25	2.25	3.00	6.33	6.33	6.33	0.00	0.00	0.00	0.00	1.00	1.00
cycles	3.00	2.50	2.25	2.25	3.00	6.33	6.33	6.33	0.00	0.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.67
Dispatch	6.33
Overall L1	8.67

Vectorization ratios

INT

all	16%
load	20%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	16%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	13%
load	15%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	13%
load	14%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.67 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.15 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4bfad0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVSXD %ESI,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x210(%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x10(%RAX),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 51ed20 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV 0x278(%R12),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA 0x128(%R12),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV (%RDI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CALLQ 0x30(%RCX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	0	0	2.20
MOV 0x1e0(%R12),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CMP %RSI,0x1e8(%R12)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JE 4bfb5c <_ZN11qmcplusplus11ParticleSet10acceptMoveEi+0x8c>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0x40(%R12),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVDQU 0x128(%R12),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
LEA (%R14,%R14,2),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x68(%R12),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%R9,%R8,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVDQU %XMM1,(%R10)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x138(%R12),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R11,0x10(%R10)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVSD 0x140(%R12),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM0,(%RAX,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVL $-0x1,0x124(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CALL 51ef50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
ADD $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 40632a <_ZN11qmcplusplus11ParticleSet10acceptMoveEi.cold>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	1	0	1	0	1	0	1	0	0	0	0	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	1	1	1	1	0	0.01
2x2	2	1	1	1.5	0	0
2x4	4	1	1	2.25	0	0
2x8	8	1	1	4	0	0
2x16	17	1	1	8.25	0	0
2x32	43	1	1	16.5	0.01	0
2x64	101	0	0	32.5	0.02	0
2x96	181	0	0	48.5	0.03	0

Name	Coverage (%)	Time (s)
▼_ZN11qmcplusplus11ParticleSet10acceptMoveEi–	0.01	0
○Loop 1251 - stl_vector.h:990-990 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency