OV - - Function _ZN11qmcplusplus16BsplineAllocatorIdLm64ENS_10MallocatorIdLm64EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp

	Function: _ZN11qmcplusplus16BsplineAllocatorIdLm64ENS_10MallocatorIdLm64EEEE26setCoefficientsForOrbi ...	Module: exec	Source: BsplineAllocator.hpp:171-180 [...]	Coverage: 0.08%

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/BsplineAllocator.hpp: 171 - 180

--------------------------------------------------------------------------------

171: #pragma omp parallel for collapse(3)

172:   for (int ix = 0; ix < spline->x_grid.num + 3; ix++)

173:     for (int iy = 0; iy < spline->y_grid.num + 3; iy++)

174:       for (int iz = 0; iz < spline->z_grid.num + 3; iz++)

175:       {

176:         intptr_t xs = spline->x_stride;

177:         intptr_t ys = spline->y_stride;

178:         intptr_t zs = spline->z_stride;

179:         for (int ind = first; ind < last; ind++)

180:           spline->coefs[ix * xs + iy * ys + iz * zs + ind] = coeff(ix, iy, iz) * prefactor[ind];

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsArray.h: 156 - 156

--------------------------------------------------------------------------------

156:     return X[k + Length[2] * (j + Length[1] * i)];

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h: 1126 - 1126

--------------------------------------------------------------------------------

1126: 	return *(this->_M_impl._M_start + __n);

0x476d10 PUSH	%RBP

0x476d11 MOV	%RSP,%RBP

0x476d14 PUSH	%R15

0x476d16 PUSH	%R14

0x476d18 PUSH	%R13

0x476d1a PUSH	%R12

0x476d1c PUSH	%RBX

0x476d1d MOV	%RDI,%R12

0x476d20 AND	$-0x40,%RSP

0x476d24 ADD	$-0x80,%RSP

0x476d28 MOV	0x8(%RDI),%R13

0x476d2c MOV	0x38(%R13),%EAX

0x476d30 MOV	0x60(%R13),%EDX

0x476d34 MOV	0x88(%R13),%EDI

0x476d3b ADD	$0x3,%EDX

0x476d3e LEA	0x3(%RDI),%R15D

0x476d42 LEA	0x3(%RAX),%EBX

0x476d45 MOV	%EDX,0x54(%RSP)

0x476d49 MOV	%R15D,0x70(%RSP)

0x476d4e TEST	%EBX,%EBX

0x476d50 JLE	4771b3

0x476d56 TEST	%EDX,%EDX

0x476d58 JLE	4771b3

0x476d5e IMUL	%EDX,%EBX

0x476d61 TEST	%R15D,%R15D

0x476d64 JLE	4771b3

0x476d6a CALL	4044a0 <omp_get_num_threads@plt>

0x476d6f MOV	%EAX,%R14D

0x476d72 CALL	4044e0 <omp_get_thread_num@plt>

0x476d77 XOR	%EDX,%EDX

0x476d79 MOV	%EAX,%ECX

0x476d7b MOV	%R15D,%EAX

0x476d7e IMUL	%EBX,%EAX

0x476d81 DIV	%R14D

0x476d84 MOV	%EAX,%ESI

0x476d86 CMP	%EDX,%ECX

0x476d88 JB	477395

0x476d8e IMUL	%ESI,%ECX

0x476d91 LEA	(%RCX,%RDX,1),%EAX

0x476d94 LEA	(%RSI,%RAX,1),%R8D

0x476d98 CMP	%R8D,%EAX

0x476d9b JAE	4771b3

0x476da1 XOR	%EDX,%EDX

0x476da3 MOV	0x1c(%R12),%R9D

0x476da8 MOV	0x18(%R12),%R10D

0x476dad MOV	(%R12),%R11

0x476db1 DIVL	0x70(%RSP)

0x476db5 VMOVQ	0x10(%R13),%XMM8

0x476dbb VMOVQ	0x18(%R13),%XMM9

0x476dc1 MOV	0x10(%R12),%R12

0x476dc6 VMOVQ	0x20(%R13),%XMM10

0x476dcc MOV	%R9D,0x44(%RSP)

0x476dd1 MOV	%R10D,0x38(%RSP)

0x476dd6 MOV	%EDX,%R8D

0x476dd9 XOR	%EDX,%EDX

0x476ddb DIVL	0x54(%RSP)

0x476ddf MOV	%EDX,0x5c(%RSP)

0x476de3 MOV	%EAX,0x3c(%RSP)

0x476de7 CMP	%R10D,%R9D

0x476dea JLE	4771b3

0x476df0 MOV	(%R12),%RDX

0x476df4 SUB	%R10D,%R9D

0x476df7 MOVSXD	%R10D,%RBX

0x476dfa DEC	%ESI

0x476dfc VMOVD	%R9D,%XMM0

0x476e01 LEA	0x8(,%RBX,8),%RCX

0x476e09 VMOVQ	0x18(%R11),%XMM5

0x476e0f MOV	%ESI,0x64(%RSP)

0x476e13 VMOVQ	%XMM0,%R15

0x476e18 MOV	0x8(%R13),%R14

0x476e1c VMOVQ	0x10(%R11),%XMM12

0x476e22 VMOVQ	0x8(%R11),%XMM11

0x476e28 MOV	%R15D,%ESI

0x476e2b MOV	%R15D,%R12D

0x476e2e MOVSXD	0x5c(%RSP),%R11

0x476e33 LEA	-0x1(%R15),%R13D

0x476e37 AND	$-0x8,%R12D

0x476e3b MOV	%R13D,0x74(%RSP)

0x476e40 MOV	%R15D,%R13D

0x476e43 VMOVD	%XMM0,0x34(%RSP)

0x476e49 LEA	(%RDX,%RCX,1),%RDI

0x476e4d LEA	-0x8(%RDX,%RCX,1),%R9

0x476e52 MOVSXD	0x3c(%RSP),%RCX

0x476e57 LEA	(%R12,%R10,1),%EAX

0x476e5b VMOVQ	%RDI,%XMM13

0x476e60 VMOVQ	%XMM0,%R10

0x476e65 SUB	%R12D,%R15D

0x476e68 AND	$0x7,%R13D

0x476e6c SHR	$0x3,%ESI

0x476e6f MOV	%R15D,0x50(%RSP)

0x476e74 MOV	%R12D,0x40(%RSP)

0x476e79 MOV	%R13D,0x58(%RSP)

0x476e7e VMOVDQA	%XMM8,%XMM1

0x476e82 VMOVDQA	%XMM9,%XMM3

0x476e86 MOV	%EAX,0x48(%RSP)

0x476e8a MOV	%ESI,%EDI

0x476e8c LEA	-0x1(%R15),%R15D

0x476e90 MOV	%RBX,%R13

0x476e93 VMOVDQA	%XMM10,%XMM4

0x476e97 SAL	$0x6,%RDI

0x476e9b MOV	%R15D,0x4c(%RSP)

0x476ea0 VMOVQ	%RCX,%XMM6

0x476ea5 VMOVQ	%XMM5,%R12

0x476eaa SAL	$0x3,%R10

0x476eae MOV	%RDI,0x68(%RSP)

0x476eb3 MOV	%R10,0x78(%RSP)

0x476eb8 MOV	%R9,%R15

0x476ebb XOR	%R10D,%R10D

0x476ebe MOV	%R14,%RBX

0x476ec1 MOV	%RDX,%RDI

0x476ec4 NOPW	%CS:(%RAX,%RAX,1)

0x476ecf NOP

(824) 0x476ed0 VMOVQ	%XMM11,%RDX

(824) 0x476ed5 VMOVQ	%XMM6,%RAX

(824) 0x476eda MOVSXD	%R8D,%RSI

(824) 0x476edd IMUL	%RDX,%RAX

(824) 0x476ee1 VMOVQ	%XMM12,%R14

(824) 0x476ee6 VMOVQ	%XMM1,%R9

(824) 0x476eeb VMOVQ	%XMM6,%RCX

(824) 0x476ef0 IMUL	%R9,%RCX

(824) 0x476ef4 VMOVQ	%XMM3,%R9

(824) 0x476ef9 ADD	%R11,%RAX

(824) 0x476efc IMUL	%R11,%R9

(824) 0x476f00 IMUL	%R14,%RAX

(824) 0x476f04 VMOVQ	%XMM4,%R14

(824) 0x476f09 ADD	%R9,%RCX

(824) 0x476f0c ADD	%RSI,%RAX

(824) 0x476f0f IMUL	%R14,%RSI

(824) 0x476f13 SAL	$0x3,%RAX

(824) 0x476f17 CMPL	$0x2,0x74(%RSP)

(824) 0x476f1c LEA	(%R12,%RAX,1),%RDX

(824) 0x476f20 LEA	(%RCX,%RSI,1),%R9

(824) 0x476f24 JBE	4771d0

(824) 0x476f2a ADD	%R13,%RSI

(824) 0x476f2d VMOVQ	%XMM0,%R14

(824) 0x476f32 LEA	0x8(%R12,%RAX,1),%RAX

(824) 0x476f37 ADD	%RSI,%RCX

(824) 0x476f3a ADD	%RCX,%R14

(824) 0x476f3d LEA	(%RBX,%RCX,8),%RSI

(824) 0x476f41 LEA	(%RBX,%R14,8),%R14

(824) 0x476f45 CMP	%R14,%RDX

(824) 0x476f48 SETAE	%R14B

(824) 0x476f4c CMP	%RAX,%RSI

(824) 0x476f4f SETAE	%AL

(824) 0x476f52 OR	%R14B,%AL

(824) 0x476f55 JE	4771d0

(824) 0x476f5b MOV	%RSI,%RAX

(824) 0x476f5e VMOVQ	%XMM13,%R14

(824) 0x476f63 SUB	%R14,%RAX

(824) 0x476f66 CMP	$0x30,%RAX

(824) 0x476f6a JBE	4771d0

(824) 0x476f70 CMPL	$0x6,0x74(%RSP)

(824) 0x476f75 JBE	47739e

(824) 0x476f7b MOV	0x68(%RSP),%R14

(824) 0x476f80 XOR	%EAX,%EAX

(824) 0x476f82 VBROADCASTSD	(%RDX),%ZMM2

(824) 0x476f88 SUB	$0x40,%R14

(824) 0x476f8c SHR	$0x6,%R14

(824) 0x476f90 INC	%R14

(824) 0x476f93 AND	$0x7,%R14D

(824) 0x476f97 JE	477050

(824) 0x476f9d CMP	$0x1,%R14

(824) 0x476fa1 JE	477030

(824) 0x476fa7 CMP	$0x2,%R14

(824) 0x476fab JE	47701e

(824) 0x476fad CMP	$0x3,%R14

(824) 0x476fb1 JE	47700c

(824) 0x476fb3 CMP	$0x4,%R14

(824) 0x476fb7 JE	476ffa

(824) 0x476fb9 CMP	$0x5,%R14

(824) 0x476fbd JE	476fe8

(824) 0x476fbf CMP	$0x6,%R14

(824) 0x476fc3 JE	476fd6

(824) 0x476fc5 VMULPD	(%R15),%ZMM2,%ZMM14

(824) 0x476fcb MOV	$0x40,%EAX

(824) 0x476fd0 VMOVUPD	%ZMM14,(%RSI)

(824) 0x476fd6 VMULPD	(%R15,%RAX,1),%ZMM2,%ZMM7

(824) 0x476fdd VMOVUPD	%ZMM7,(%RSI,%RAX,1)

(824) 0x476fe4 ADD	$0x40,%RAX

(824) 0x476fe8 VMULPD	(%R15,%RAX,1),%ZMM2,%ZMM15

(824) 0x476fef VMOVUPD	%ZMM15,(%RSI,%RAX,1)

(824) 0x476ff6 ADD	$0x40,%RAX

(824) 0x476ffa VMULPD	(%R15,%RAX,1),%ZMM2,%ZMM8

(824) 0x477001 VMOVUPD	%ZMM8,(%RSI,%RAX,1)

(824) 0x477008 ADD	$0x40,%RAX

(824) 0x47700c VMULPD	(%R15,%RAX,1),%ZMM2,%ZMM9

(824) 0x477013 VMOVUPD	%ZMM9,(%RSI,%RAX,1)

(824) 0x47701a ADD	$0x40,%RAX

(824) 0x47701e VMULPD	(%R15,%RAX,1),%ZMM2,%ZMM10

(824) 0x477025 VMOVUPD	%ZMM10,(%RSI,%RAX,1)

(824) 0x47702c ADD	$0x40,%RAX

(824) 0x477030 VMULPD	(%R15,%RAX,1),%ZMM2,%ZMM5

(824) 0x477037 MOV	0x68(%RSP),%R14

(824) 0x47703c VMOVUPD	%ZMM5,(%RSI,%RAX,1)

(824) 0x477043 ADD	$0x40,%RAX

(824) 0x477047 CMP	%R14,%RAX

(824) 0x47704a JE	4770e2

  (825) 0x477050 VMULPD	(%R15,%RAX,1),%ZMM2,%ZMM14

  (825) 0x477057 MOV	0x68(%RSP),%R14

  (825) 0x47705c VMOVUPD	%ZMM14,(%RSI,%RAX,1)

  (825) 0x477063 VMULPD	0x40(%R15,%RAX,1),%ZMM2,%ZMM7

  (825) 0x47706b VMOVUPD	%ZMM7,0x40(%RSI,%RAX,1)

  (825) 0x477073 VMULPD	0x80(%R15,%RAX,1),%ZMM2,%ZMM15

  (825) 0x47707b VMOVUPD	%ZMM15,0x80(%RSI,%RAX,1)

  (825) 0x477083 VMULPD	0xc0(%R15,%RAX,1),%ZMM2,%ZMM8

  (825) 0x47708b VMOVUPD	%ZMM8,0xc0(%RSI,%RAX,1)

  (825) 0x477093 VMULPD	0x100(%R15,%RAX,1),%ZMM2,%ZMM9

  (825) 0x47709b VMOVUPD	%ZMM9,0x100(%RSI,%RAX,1)

  (825) 0x4770a3 VMULPD	0x140(%R15,%RAX,1),%ZMM2,%ZMM10

  (825) 0x4770ab VMOVUPD	%ZMM10,0x140(%RSI,%RAX,1)

  (825) 0x4770b3 VMULPD	0x180(%R15,%RAX,1),%ZMM2,%ZMM5

  (825) 0x4770bb VMOVUPD	%ZMM5,0x180(%RSI,%RAX,1)

  (825) 0x4770c3 VMULPD	0x1c0(%R15,%RAX,1),%ZMM2,%ZMM14

  (825) 0x4770cb VMOVUPD	%ZMM14,0x1c0(%RSI,%RAX,1)

  (825) 0x4770d3 ADD	$0x200,%RAX

  (825) 0x4770d9 CMP	%R14,%RAX

  (825) 0x4770dc JNE	477050

(824) 0x4770e2 MOV	0x58(%RSP),%ESI

(824) 0x4770e6 TEST	%ESI,%ESI

(824) 0x4770e8 JE	47718e

(824) 0x4770ee CMPL	$0x2,0x4c(%RSP)

(824) 0x4770f3 MOV	0x50(%RSP),%ESI

(824) 0x4770f7 JBE	4773b1

(824) 0x4770fd MOV	0x48(%RSP),%R14D

(824) 0x477102 MOV	0x40(%RSP),%EAX

(824) 0x477106 MOV	%R14D,0x60(%RSP)

(824) 0x47710b LEA	(%R13,%RAX,1),%R14

(824) 0x477110 VBROADCASTSD	(%RDX),%YMM2

(824) 0x477115 ADD	%RCX,%RAX

(824) 0x477118 MOV	0x60(%RSP),%ECX

(824) 0x47711c VMULPD	(%RDI,%R14,8),%YMM2,%YMM7

(824) 0x477122 VMOVUPD	%YMM7,(%RBX,%RAX,8)

(824) 0x477127 MOV	%ESI,%EAX

(824) 0x477129 AND	$-0x4,%EAX

(824) 0x47712c ADD	%ECX,%EAX

(824) 0x47712e AND	$0x3,%ESI

(824) 0x477131 JE	47718e

(824) 0x477133 MOVSXD	%EAX,%R14

(824) 0x477136 LEA	0x1(%RAX),%ECX

(824) 0x477139 LEA	(,%R14,8),%RSI

(824) 0x477141 ADD	%R9,%R14

(824) 0x477144 VMOVSD	(%RDI,%RSI,1),%XMM15

(824) 0x477149 VMULSD	(%RDX),%XMM15,%XMM8

(824) 0x47714d VMOVSD	%XMM8,(%RBX,%R14,8)

(824) 0x477153 MOV	0x44(%RSP),%R14D

(824) 0x477158 CMP	%ECX,%R14D

(824) 0x47715b JLE	47718e

(824) 0x47715d MOVSXD	%ECX,%RCX

(824) 0x477160 ADD	$0x2,%EAX

(824) 0x477163 VMOVSD	0x8(%RDI,%RSI,1),%XMM9

(824) 0x477169 VMULSD	(%RDX),%XMM9,%XMM10

(824) 0x47716d ADD	%R9,%RCX

(824) 0x477170 VMOVSD	%XMM10,(%RBX,%RCX,8)

(824) 0x477175 CMP	%EAX,%R14D

(824) 0x477178 JLE	47718e

(824) 0x47717a CLTQ

(824) 0x47717c VMOVSD	0x10(%RDI,%RSI,1),%XMM5

(824) 0x477182 VMULSD	(%RDX),%XMM5,%XMM14

(824) 0x477186 ADD	%R9,%RAX

(824) 0x477189 VMOVSD	%XMM14,(%RBX,%RAX,8)

(824) 0x47718e MOV	0x64(%RSP),%EDX

(824) 0x477192 CMP	%EDX,%R10D

(824) 0x477195 JE	4771b0

(824) 0x477197 INC	%R8D

(824) 0x47719a CMP	%R8D,0x70(%RSP)

(824) 0x47719f JLE	477360

(824) 0x4771a5 INC	%R10D

(824) 0x4771a8 JMP	476ed0

0x4771ad NOPL	(%RAX)

0x4771b0 VZEROUPPER

0x4771b3 LEA	-0x28(%RBP),%RSP

0x4771b7 POP	%RBX

0x4771b8 POP	%R12

0x4771ba POP	%R13

0x4771bc POP	%R14

0x4771be POP	%R15

0x4771c0 POP	%RBP

0x4771c1 RET

0x4771c2 NOPW	%CS:(%RAX,%RAX,1)

0x4771cd NOPL	(%RAX)

(824) 0x4771d0 MOV	0x78(%RSP),%RSI

(824) 0x4771d5 ADD	%R13,%R9

(824) 0x4771d8 XOR	%EAX,%EAX

(824) 0x4771da LEA	(%RBX,%R9,8),%R9

(824) 0x4771de SUB	$0x8,%RSI

(824) 0x4771e2 SHR	$0x3,%RSI

(824) 0x4771e6 INC	%RSI

(824) 0x4771e9 AND	$0x7,%ESI

(824) 0x4771ec JE	4772b0

(824) 0x4771f2 CMP	$0x1,%RSI

(824) 0x4771f6 JE	477291

(824) 0x4771fc CMP	$0x2,%RSI

(824) 0x477200 JE	47727d

(824) 0x477202 CMP	$0x3,%RSI

(824) 0x477206 JE	477269

(824) 0x477208 CMP	$0x4,%RSI

(824) 0x47720c JE	477255

(824) 0x47720e CMP	$0x5,%RSI

(824) 0x477212 JE	477241

(824) 0x477214 CMP	$0x6,%RSI

(824) 0x477218 JE	47722d

(824) 0x47721a MOV	$0x8,%EAX

(824) 0x47721f VMOVSD	(%R15),%XMM2

(824) 0x477224 VMULSD	(%RDX),%XMM2,%XMM7

(824) 0x477228 VMOVSD	%XMM7,(%R9)

(824) 0x47722d VMOVSD	(%R15,%RAX,1),%XMM15

(824) 0x477233 VMULSD	(%RDX),%XMM15,%XMM8

(824) 0x477237 VMOVSD	%XMM8,(%R9,%RAX,1)

(824) 0x47723d ADD	$0x8,%RAX

(824) 0x477241 VMOVSD	(%R15,%RAX,1),%XMM9

(824) 0x477247 VMULSD	(%RDX),%XMM9,%XMM10

(824) 0x47724b VMOVSD	%XMM10,(%R9,%RAX,1)

(824) 0x477251 ADD	$0x8,%RAX

(824) 0x477255 VMOVSD	(%R15,%RAX,1),%XMM5

(824) 0x47725b VMULSD	(%RDX),%XMM5,%XMM14

(824) 0x47725f VMOVSD	%XMM14,(%R9,%RAX,1)

(824) 0x477265 ADD	$0x8,%RAX

(824) 0x477269 VMOVSD	(%R15,%RAX,1),%XMM2

(824) 0x47726f VMULSD	(%RDX),%XMM2,%XMM7

(824) 0x477273 VMOVSD	%XMM7,(%R9,%RAX,1)

(824) 0x477279 ADD	$0x8,%RAX

(824) 0x47727d VMOVSD	(%R15,%RAX,1),%XMM15

(824) 0x477283 VMULSD	(%RDX),%XMM15,%XMM8

(824) 0x477287 VMOVSD	%XMM8,(%R9,%RAX,1)

(824) 0x47728d ADD	$0x8,%RAX

(824) 0x477291 VMOVSD	(%R15,%RAX,1),%XMM9

(824) 0x477297 VMULSD	(%RDX),%XMM9,%XMM10

(824) 0x47729b VMOVSD	%XMM10,(%R9,%RAX,1)

(824) 0x4772a1 ADD	$0x8,%RAX

(824) 0x4772a5 CMP	%RAX,0x78(%RSP)

(824) 0x4772aa JE	47718e

  (823) 0x4772b0 VMOVSD	(%R15,%RAX,1),%XMM5

  (823) 0x4772b6 VMULSD	(%RDX),%XMM5,%XMM14

  (823) 0x4772ba VMOVSD	%XMM14,(%R9,%RAX,1)

  (823) 0x4772c0 VMOVSD	0x8(%R15,%RAX,1),%XMM2

  (823) 0x4772c7 VMULSD	(%RDX),%XMM2,%XMM7

  (823) 0x4772cb VMOVSD	%XMM7,0x8(%R9,%RAX,1)

  (823) 0x4772d2 VMOVSD	0x10(%R15,%RAX,1),%XMM15

  (823) 0x4772d9 VMULSD	(%RDX),%XMM15,%XMM8

  (823) 0x4772dd VMOVSD	%XMM8,0x10(%R9,%RAX,1)

  (823) 0x4772e4 VMOVSD	0x18(%R15,%RAX,1),%XMM9

  (823) 0x4772eb VMULSD	(%RDX),%XMM9,%XMM10

  (823) 0x4772ef VMOVSD	%XMM10,0x18(%R9,%RAX,1)

  (823) 0x4772f6 VMOVSD	0x20(%R15,%RAX,1),%XMM5

  (823) 0x4772fd VMULSD	(%RDX),%XMM5,%XMM14

  (823) 0x477301 VMOVSD	%XMM14,0x20(%R9,%RAX,1)

  (823) 0x477308 VMOVSD	0x28(%R15,%RAX,1),%XMM2

  (823) 0x47730f VMULSD	(%RDX),%XMM2,%XMM7

  (823) 0x477313 VMOVSD	%XMM7,0x28(%R9,%RAX,1)

  (823) 0x47731a VMOVSD	0x30(%R15,%RAX,1),%XMM15

  (823) 0x477321 VMULSD	(%RDX),%XMM15,%XMM8

  (823) 0x477325 VMOVSD	%XMM8,0x30(%R9,%RAX,1)

  (823) 0x47732c VMOVSD	0x38(%R15,%RAX,1),%XMM9

  (823) 0x477333 VMULSD	(%RDX),%XMM9,%XMM10

  (823) 0x477337 VMOVSD	%XMM10,0x38(%R9,%RAX,1)

  (823) 0x47733e ADD	$0x40,%RAX

  (823) 0x477342 CMP	%RAX,0x78(%RSP)

  (823) 0x477347 JNE	4772b0

(824) 0x47734d JMP	47718e

0x477352 NOPW	%CS:(%RAX,%RAX,1)

0x47735d NOPL	(%RAX)

(824) 0x477360 INCL	0x5c(%RSP)

(824) 0x477364 MOVSXD	0x5c(%RSP),%R11

(824) 0x477369 XOR	%R8D,%R8D

(824) 0x47736c CMP	%R11D,0x54(%RSP)

(824) 0x477371 JG	4771a5

(824) 0x477377 INCL	0x3c(%RSP)

(824) 0x47737b MOVSXD	0x3c(%RSP),%R11

(824) 0x477380 MOVL	$0,0x5c(%RSP)

(824) 0x477388 VMOVQ	%R11,%XMM6

(824) 0x47738d XOR	%R11D,%R11D

(824) 0x477390 JMP	4771a5

0x477395 INC	%ESI

0x477397 XOR	%EDX,%EDX

0x477399 JMP	476d8e

(824) 0x47739e MOV	0x38(%RSP),%EAX

(824) 0x4773a2 MOV	0x34(%RSP),%ESI

(824) 0x4773a6 MOV	%EAX,0x60(%RSP)

(824) 0x4773aa XOR	%EAX,%EAX

(824) 0x4773ac JMP	47710b

(824) 0x4773b1 MOV	0x48(%RSP),%EAX

(824) 0x4773b5 JMP	477133

0x4773ba NOPW	(%RAX,%RAX,1)

0x49d6bd NOPL	(%RAX)

0x49d6d2 NOPW	%CS:(%RAX,%RAX,1)

0x49d6dd NOPL	(%RAX)

0x49d862 NOPW	%CS:(%RAX,%RAX,1)

0x49d86d NOPL	(%RAX)

0x49d8ca NOPW	(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	BsplineAllocator.hpp:171-180
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/BsplineAllocator.hpp:171-180
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsArray.h:156
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:1126

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.67 to 5.17 cycles (4.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 21.67 to 2.25 cycles (9.63x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences
omp_get_thread_num@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 3 occurrences
LEA: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 124 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	136
nb uops	130
loop length	549
used x86 registers	16
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.67 cycles
front end	21.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	11.50	11.50	11.50	11.50	8.00	13.00	13.00	13.00	0.00	0.00	0.00	0.00	2.00	2.00
cycles	11.50	11.50	11.50	11.50	8.00	13.00	13.00	13.00	0.00	0.00	0.00	0.00	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

18.00

Cycles summary

Front-end	21.67
Dispatch	13.00
DIV/SQRT	18.00
Overall L1	21.67

Vectorization ratios

all	8%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	22%

Vector efficiency ratios

all	9%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.67 cycles. At this rate:

5% of peak load performance is reached (5.72 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.32 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 476d10

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD $-0x80,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x8(%RDI),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x38(%R13),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x60(%R13),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x88(%R13),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD $0x3,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA 0x3(%RDI),%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA 0x3(%RAX),%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EDX,0x54(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %R15D,0x70(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
TEST %EBX,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JLE 4771b3 <_ZN11qmcplusplus16BsplineAllocatorIdLm64ENS_10MallocatorIdLm64EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x4a3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
TEST %EDX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JLE 4771b3 <_ZN11qmcplusplus16BsplineAllocatorIdLm64ENS_10MallocatorIdLm64EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x4a3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
IMUL %EDX,%EBX	1	0	1	0	0	0	0	0	0	0	0	3	1
TEST %R15D,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JLE 4771b3 <_ZN11qmcplusplus16BsplineAllocatorIdLm64ENS_10MallocatorIdLm64EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x4a3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
CALL 4044a0 <omp_get_num_threads@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %EAX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 4044e0 <omp_get_thread_num@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	3	1
DIV %R14D	2	2	0	0	0	0	0	0	0	0	0	10-17	6
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %EDX,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JB 477395 <_ZN11qmcplusplus16BsplineAllocatorIdLm64ENS_10MallocatorIdLm64EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x685>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
IMUL %ESI,%ECX	1	0	1	0	0	0	0	0	0	0	0	3	1
LEA (%RCX,%RDX,1),%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RSI,%RAX,1),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP %R8D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JAE 4771b3 <_ZN11qmcplusplus16BsplineAllocatorIdLm64ENS_10MallocatorIdLm64EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x4a3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV 0x1c(%R12),%R9D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x18(%R12),%R10D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%R12),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
DIVL 0x70(%RSP)	3	2	0	0	0	0	0.33	0.33	0.33	0	0	10-17	6
VMOVQ 0x10(%R13),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVQ 0x18(%R13),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV 0x10(%R12),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVQ 0x20(%R13),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV %R9D,0x44(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %R10D,0x38(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %EDX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
DIVL 0x54(%RSP)	3	2	0	0	0	0	0.33	0.33	0.33	0	0	10-17	6
MOV %EDX,0x5c(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %EAX,0x3c(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CMP %R10D,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JLE 4771b3 <_ZN11qmcplusplus16BsplineAllocatorIdLm64ENS_10MallocatorIdLm64EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x4a3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV (%R12),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
SUB %R10D,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSXD %R10D,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
DEC %ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVD %R9D,%XMM0	1	0	0	1	0	0	0	0	0	0	0	5	1
LEA 0x8(,%RBX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVQ 0x18(%R11),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV %ESI,0x64(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVQ %XMM0,%R15	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV 0x8(%R13),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVQ 0x10(%R11),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVQ 0x8(%R11),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVSXD 0x5c(%RSP),%R11	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
LEA -0x1(%R15),%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
AND $-0x8,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R13D,0x74(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %R15D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVD %XMM0,0x34(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	8	1
LEA (%RDX,%RCX,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA -0x8(%RDX,%RCX,1),%R9	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	2	0.50
MOVSXD 0x3c(%RSP),%RCX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
LEA (%R12,%R10,1),%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVQ %RDI,%XMM13	1	0	0	1	0	0	0	0	0	0	0	2	1
VMOVQ %XMM0,%R10	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
SUB %R12D,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
AND $0x7,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SHR $0x3,%ESI	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOV %R15D,0x50(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %R12D,0x40(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %R13D,0x58(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVDQA %XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVDQA %XMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EAX,0x48(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x1(%R15),%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVDQA %XMM10,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOV %R15D,0x4c(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVQ %RCX,%XMM6	1	0	0	1	0	0	0	0	0	0	0	2	1
VMOVQ %XMM5,%R12	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
SAL $0x3,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOV %RDI,0x68(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %R10,0x78(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV %R14,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1
LEA -0x28(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
INC %ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 476d8e <_ZN11qmcplusplus16BsplineAllocatorIdLm64ENS_10MallocatorIdLm64EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x7e>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	BsplineAllocator.hpp:171-180
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/BsplineAllocator.hpp:171-180
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsArray.h:156
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:1126

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.67 to 5.17 cycles (4.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences
omp_get_thread_num@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 3 occurrences
LEA: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 124 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	136
nb uops	130
loop length	549
used x86 registers	16
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.67 cycles
front end	21.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	11.50	11.50	11.50	11.50	8.00	13.00	13.00	13.00	0.00	0.00	0.00	0.00	2.00	2.00
cycles	11.50	11.50	11.50	11.50	8.00	13.00	13.00	13.00	0.00	0.00	0.00	0.00	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

18.00

Cycles summary

Front-end	21.67
Dispatch	13.00
DIV/SQRT	18.00
Overall L1	21.67

Vectorization ratios

all	8%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	22%

Vector efficiency ratios

all	9%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.67 cycles. At this rate:

5% of peak load performance is reached (5.72 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.32 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 476d10

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD $-0x80,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x8(%RDI),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x38(%R13),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x60(%R13),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x88(%R13),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD $0x3,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA 0x3(%RDI),%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA 0x3(%RAX),%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EDX,0x54(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %R15D,0x70(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
TEST %EBX,%EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JLE 4771b3 <_ZN11qmcplusplus16BsplineAllocatorIdLm64ENS_10MallocatorIdLm64EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x4a3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
TEST %EDX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JLE 4771b3 <_ZN11qmcplusplus16BsplineAllocatorIdLm64ENS_10MallocatorIdLm64EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x4a3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
IMUL %EDX,%EBX	1	0	1	0	0	0	0	0	0	0	0	3	1
TEST %R15D,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JLE 4771b3 <_ZN11qmcplusplus16BsplineAllocatorIdLm64ENS_10MallocatorIdLm64EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x4a3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
CALL 4044a0 <omp_get_num_threads@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %EAX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 4044e0 <omp_get_thread_num@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	3	1
DIV %R14D	2	2	0	0	0	0	0	0	0	0	0	10-17	6
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %EDX,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JB 477395 <_ZN11qmcplusplus16BsplineAllocatorIdLm64ENS_10MallocatorIdLm64EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x685>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
IMUL %ESI,%ECX	1	0	1	0	0	0	0	0	0	0	0	3	1
LEA (%RCX,%RDX,1),%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RSI,%RAX,1),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP %R8D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JAE 4771b3 <_ZN11qmcplusplus16BsplineAllocatorIdLm64ENS_10MallocatorIdLm64EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x4a3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV 0x1c(%R12),%R9D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x18(%R12),%R10D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%R12),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
DIVL 0x70(%RSP)	3	2	0	0	0	0	0.33	0.33	0.33	0	0	10-17	6
VMOVQ 0x10(%R13),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVQ 0x18(%R13),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV 0x10(%R12),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVQ 0x20(%R13),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV %R9D,0x44(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %R10D,0x38(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %EDX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
DIVL 0x54(%RSP)	3	2	0	0	0	0	0.33	0.33	0.33	0	0	10-17	6
MOV %EDX,0x5c(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %EAX,0x3c(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CMP %R10D,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JLE 4771b3 <_ZN11qmcplusplus16BsplineAllocatorIdLm64ENS_10MallocatorIdLm64EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x4a3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV (%R12),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
SUB %R10D,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSXD %R10D,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
DEC %ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVD %R9D,%XMM0	1	0	0	1	0	0	0	0	0	0	0	5	1
LEA 0x8(,%RBX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVQ 0x18(%R11),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV %ESI,0x64(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVQ %XMM0,%R15	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOV 0x8(%R13),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVQ 0x10(%R11),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVQ 0x8(%R11),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVSXD 0x5c(%RSP),%R11	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
LEA -0x1(%R15),%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
AND $-0x8,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R13D,0x74(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %R15D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVD %XMM0,0x34(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	8	1
LEA (%RDX,%RCX,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA -0x8(%RDX,%RCX,1),%R9	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	2	0.50
MOVSXD 0x3c(%RSP),%RCX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
LEA (%R12,%R10,1),%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVQ %RDI,%XMM13	1	0	0	1	0	0	0	0	0	0	0	2	1
VMOVQ %XMM0,%R10	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
SUB %R12D,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
AND $0x7,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SHR $0x3,%ESI	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOV %R15D,0x50(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %R12D,0x40(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %R13D,0x58(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVDQA %XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVDQA %XMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EAX,0x48(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x1(%R15),%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVDQA %XMM10,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOV %R15D,0x4c(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVQ %RCX,%XMM6	1	0	0	1	0	0	0	0	0	0	0	2	1
VMOVQ %XMM5,%R12	1	0	0	0	0	0	0	0	0	0.50	0.50	1	1
SAL $0x3,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOV %RDI,0x68(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %R10,0x78(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV %R14,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1
LEA -0x28(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
INC %ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 476d8e <_ZN11qmcplusplus16BsplineAllocatorIdLm64ENS_10MallocatorIdLm64EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0+0x7e>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.89	0.01	0.89	0	0.5	0.01	0.48	0.01	0.24	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.04	0.08
2x2	4	0.89	1.33	1.5	0.05	0.06
2x4	8	0.89	2	2.25	0.02	0.04
2x8	16	0.5	2	4	0.02	0.03
2x16	32	0.48	4	8.25	0.03	0.01
2x32	64	0.24	4	16.5	0.02	0
2x64	52	1	1	32.5	0.01	0
2x96	67	1	1	48.5	0.01	0

Name	Coverage (%)	Time (s)
▼_ZN11qmcplusplus16BsplineAllocatorIdLm64ENS_10MallocatorIdLm64EEEE26setCoefficientsForOrbitalsEiiR5ArrayIdLj3EEP19multi_UBspline_3d_d._omp_fn.0–	0.08	0.04
▼Loop 824 - BsplineAllocator.hpp:171-180 - exec–	0	0
○Loop 825 - BsplineAllocator.hpp:179-180 - exec	0.08	0.04
○Loop 823 - BsplineAllocator.hpp:179-180 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency