OV - - Function _ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE8evalGradERNS1

	Function: _ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE8evalGradERNS1 ...	Module: exec	Source: TwoBodyJastrowRef.h:291-294 [...]	Coverage: 0.01%

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 231

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 144 - 145

--------------------------------------------------------------------------------

144:     for (int i = 0; i < D; ++i)

145:       X[i] = base[i * offset];

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 291 - 294

--------------------------------------------------------------------------------

291: typename TwoBodyJastrowRef<FT>::GradType TwoBodyJastrowRef<FT>::evalGrad(ParticleSet& P, int iat)

292: {

293:   return GradType(dUat[iat]);

294: }

0x4201d0 MOV	%RDI,%RDX

0x4201d3 MOV	0xf0(%RSI),%RDI

0x4201da MOV	0x100(%RSI),%RAX

0x4201e1 MOVSXD	%ECX,%RCX

0x4201e4 CMP	$0x1,%RDI

0x4201e8 JNE	420210

0x4201ea VMOVSD	(%RAX,%RCX,8),%XMM2

0x4201ef VMOVHPD	0x8(%RAX,%RCX,8),%XMM2,%XMM3

0x4201f5 VMOVSD	0x10(%RAX,%RCX,8),%XMM4

0x4201fb MOV	%RDX,%RAX

0x4201fe VMOVUPD	%XMM3,(%RDX)

0x420202 VMOVSD	%XMM4,0x10(%RDX)

0x420207 RET

0x420208 NOPL	(%RAX,%RAX,1)

0x420210 MOVSXD	%EDI,%R8

0x420213 ADD	%EDI,%EDI

0x420215 LEA	(%RAX,%RCX,8),%RSI

0x420219 MOVSXD	%EDI,%R9

0x42021c VMOVSD	(%RSI),%XMM0

0x420220 VMOVHPD	(%RSI,%R8,8),%XMM0,%XMM1

0x420226 ADD	%RCX,%R9

0x420229 VMOVUPD	%XMM1,(%RDX)

0x42022d VMOVSD	(%RAX,%R9,8),%XMM4

0x420233 MOV	%RDX,%RAX

0x420236 VMOVSD	%XMM4,0x10(%RDX)

0x42023b RET

0x42023c NOPL	(%RAX)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	TwoBodyJastrowRef.h:291-294
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:144-145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:291-294

The structure of this function is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 2.67 to 0.54 cycles (4.92x speedup).

Details

16% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	15.50
nb uops	15.50
loop length	63
used x86 registers	6
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	2.58 cycles
front end	2.58 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.50	1.38	1.38	1.25	1.00	2.33	2.33	2.33	0.00	0.33	0.33	0.33	1.00	1.00
cycles	1.50	1.38	1.38	1.25	1.00	2.33	2.33	2.33	0.00	0.33	0.33	0.33	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.58
Dispatch	2.33
Overall L1	2.67

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	20%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	16%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	15%
load	12%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	12%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 2.67 cycles. At this rate:

15% of peak load performance is reached (15.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (9.14 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Source file and lines	TwoBodyJastrowRef.h:291-294
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:144-145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:291-294

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.33 to 2.00 cycles (1.17x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 2.33 to 0.54 cycles (4.31x speedup).

Details

20% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 2.33 to 2.17 cycles (1.08x speedup).

Workaround

Read less array elements
Write less array elements

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	13
nb uops	13
loop length	56
used x86 registers	5
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.17 cycles
front end	2.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	0.75	0.75	0.50	1.00	2.33	2.33	2.33	0.00	0.33	0.33	0.33	1.00	1.00
cycles	1.00	0.75	0.75	0.50	1.00	2.33	2.33	2.33	0.00	0.33	0.33	0.33	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.17
Dispatch	2.33
Overall L1	2.33

Vectorization ratios

all	20%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	15%
load	12%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 2.33 cycles. At this rate:

17% of peak load performance is reached (17.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (10.29 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4201d0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xf0(%RSI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	0.33
MOV 0x100(%RSI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	0.33
MOVSXD %ECX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x1,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
JNE 420210 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE8evalGradERNS1_11ParticleSetEi+0x40>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD (%RAX,%RCX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD 0x8(%RAX,%RCX,8),%XMM2,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
VMOVSD 0x10(%RAX,%RCX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVUPD %XMM3,(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD %XMM4,0x10(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	TwoBodyJastrowRef.h:291-294
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:144-145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:291-294

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.00 to 1.67 cycles (1.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 3.00 to 0.54 cycles (5.54x speedup).

Details

12% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	18
nb uops	18
loop length	70
used x86 registers	7
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.00	2.00	2.00	2.00	1.00	2.33	2.33	2.33	0.00	0.33	0.33	0.33	1.00	1.00
cycles	2.00	2.00	2.00	2.00	1.00	2.33	2.33	2.33	0.00	0.33	0.33	0.33	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.00
Dispatch	2.33
Overall L1	3.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	20%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	15%
load	12%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	13%
load	12%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.00 cycles. At this rate:

13% of peak load performance is reached (13.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (8.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 2.33 cycles (1.29x speedup).

ASM code

In the binary file, the address of the function is: 4201d0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xf0(%RSI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	0.33
MOV 0x100(%RSI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	0.33
MOVSXD %ECX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x1,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
JNE 420210 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE8evalGradERNS1_11ParticleSetEi+0x40>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %EDI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EDI,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RAX,%RCX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %EDI,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RSI),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%RSI,%R8,8),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
ADD %RCX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %XMM1,(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD (%RAX,%R9,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD %XMM4,0x10(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	0.50

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0			1	0	1	0	1	0	0	0	0	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	1	1	1	1	0	0.01
2x2	1	1	1	1.5	0	0
2x4
2x8	3	1	1	4	0	0
2x16	8	1	1	8.25	0	0
2x32	25	1	1	16.5	0.01	0
2x64	92	0	0	32.5	0.02	0
2x96	150	0	0	48.5	0.03	0

Name	Coverage (%)	Time (s)
○_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE8evalGradERNS1_11ParticleSetEi	0.01	0

Report Configuration

Vectorization

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency