OV - - Function _ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE6updateEi

	Function: _ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE6updateEi	Module: exec	Source: SoaDistanceTableABOMPTarget.h:371-377 [...]	Coverage: NA%

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 271 - 271

--------------------------------------------------------------------------------

271:   inline T* restrict data(size_t i) { return myData + i * nGhosts; }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algo.h: 731 - 757

--------------------------------------------------------------------------------

731:     { return std::copy(__first, __first + __n, __result); }

[...]

757:       if (__n2 <= 0)

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 248 - 248

--------------------------------------------------------------------------------

248:   inline pointer data() { return X; }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h: 371 - 377

--------------------------------------------------------------------------------

371:   inline void update(IndexType iat) override

372:   {

373:     ScopedTimer local_timer(update_timer_);

374:     std::copy_n(temp_r_.data(), num_sources_, distances_[iat].data());

375:     for (int idim = 0; idim < D; ++idim)

376:       std::copy_n(temp_dr_.data(idim), num_sources_, displacements_[iat].data(idim));

377:   }

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h: 1126 - 1126

--------------------------------------------------------------------------------

1126: 	return *(this->_M_impl._M_start + __n);

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algobase.h: 398 - 438

--------------------------------------------------------------------------------

398: 	{ *__to = *__from; }

[...]

436: 	  if (__builtin_expect(_Num > 1, true))

437: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

438: 	  else if (_Num == 1)

0x57c180 PUSH	%RBP

0x57c181 MOV	%RSP,%RBP

0x57c184 PUSH	%R14

0x57c186 PUSH	%R13

0x57c188 PUSH	%R12

0x57c18a PUSH	%RBX

0x57c18b MOV	0x1c8(%RDI),%R12

0x57c192 MOV	%RDI,%R13

0x57c195 MOVSXD	%ESI,%RBX

0x57c198 LEA	(%RBX,%RBX,4),%RBX

0x57c19c SAL	$0x3,%RBX

0x57c1a0 MOV	%R12,%RDI

0x57c1a3 CALL	51ed20 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x57c1a8 MOV	0x10(%R13),%RAX

0x57c1ac TEST	%RAX,%RAX

0x57c1af JE	57c1dc

0x57c1b1 MOV	0x48(%R13),%RDX

0x57c1b5 MOV	0x90(%R13),%RSI

0x57c1bc MOV	0x18(%RDX,%RBX,1),%RDI

0x57c1c1 LEA	(,%RAX,8),%RDX

0x57c1c9 CMP	$0x8,%RDX

0x57c1cd JLE	57c270

0x57c1d3 CALL	4040d0 <memmove@plt>

0x57c1d8 MOV	0x10(%R13),%RAX

0x57c1dc XOR	%R14D,%R14D

0x57c1df TEST	%RAX,%RAX

0x57c1e2 JE	57c224

(2548) 0x57c1e4 MOV	0x60(%R13),%RSI

(2548) 0x57c1e8 MOV	0xa8(%R13),%R8

(2548) 0x57c1ef MOV	0xb8(%R13),%R9

(2548) 0x57c1f6 LEA	(,%RAX,8),%RDX

(2548) 0x57c1fe ADD	%RBX,%RSI

(2548) 0x57c201 IMUL	%R14,%R8

(2548) 0x57c205 MOV	0x8(%RSI),%RCX

(2548) 0x57c209 MOV	0x18(%RSI),%RDI

(2548) 0x57c20d LEA	(%R9,%R8,8),%RSI

(2548) 0x57c211 IMUL	%R14,%RCX

(2548) 0x57c215 LEA	(%RDI,%RCX,8),%RDI

(2548) 0x57c219 CMP	$0x8,%RDX

(2548) 0x57c21d JLE	57c260

(2548) 0x57c21f CALL	4040d0 <memmove@plt>

(2548) 0x57c224 INC	%R14

(2548) 0x57c227 CMP	$0x3,%R14

(2548) 0x57c22b JE	57c240

(2548) 0x57c22d MOV	0x10(%R13),%RAX

(2548) 0x57c231 TEST	%RAX,%RAX

(2548) 0x57c234 JNE	57c1e4

(2548) 0x57c236 JMP	57c224

0x57c238 NOPL	(%RAX,%RAX,1)

0x57c240 MOV	%R12,%RDI

0x57c243 CALL	51ef50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x57c248 POP	%RBX

0x57c249 POP	%R12

0x57c24b POP	%R13

0x57c24d POP	%R14

0x57c24f POP	%RBP

0x57c250 RET

0x57c251 NOPW	%CS:(%RAX,%RAX,1)

0x57c25c NOPL	(%RAX)

(2548) 0x57c260 JNE	57c224

(2548) 0x57c262 VMOVSD	(%RSI),%XMM1

(2548) 0x57c266 VMOVSD	%XMM1,(%RDI)

(2548) 0x57c26a JMP	57c224

0x57c26c NOPL	(%RAX)

0x57c270 JNE	57c1dc

0x57c276 VMOVSD	(%RSI),%XMM0

0x57c27a VMOVSD	%XMM0,(%RDI)

0x57c27e JMP	57c1dc

0x57c283 NOPW	%CS:(%RAX,%RAX,1)

0x57c28d NOPL	(%RAX)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	SoaDistanceTableABOMPTarget.h:371-377
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:271
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algo.h:731,757
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:248
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:371-377
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:1126
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algobase.h:398,436-438

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 2.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 7.00 to 0.69 cycles (10.18x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv: 1 occurrences
_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv: 1 occurrences
memmove@plt: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	45
nb uops	42
loop length	176
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.50	2.50	2.25	2.25	4.50	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.50	0.50
cycles	4.50	2.50	2.25	2.25	4.50	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.00
Dispatch	4.50
Overall L1	7.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.14 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.00 to 4.50 cycles (1.56x speedup).

ASM code

In the binary file, the address of the function is: 57c180

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x1c8(%RDI),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVSXD %ESI,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RBX,%RBX,4),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SAL $0x3,%RBX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 51ed20 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV 0x10(%R13),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
TEST %RAX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 57c1dc <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE6updateEi+0x5c>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV 0x48(%R13),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x90(%R13),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x18(%RDX,%RBX,1),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (,%RAX,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP $0x8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JLE 57c270 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE6updateEi+0xf0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
CALL 4040d0 <memmove@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV 0x10(%R13),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.25
TEST %RAX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 57c224 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE6updateEi+0xa4>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 51ef50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
JNE 57c1dc <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE6updateEi+0x5c>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
VMOVSD (%RSI),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM0,(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
JMP 57c1dc <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE6updateEi+0x5c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	SoaDistanceTableABOMPTarget.h:371-377
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:271
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algo.h:731,757
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:248
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:371-377
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:1126
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algobase.h:398,436-438

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 2.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv: 1 occurrences
_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv: 1 occurrences
memmove@plt: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	45
nb uops	42
loop length	176
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.50	2.50	2.25	2.25	4.50	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.50	0.50
cycles	4.50	2.50	2.25	2.25	4.50	3.67	3.67	3.67	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.00
Dispatch	4.50
Overall L1	7.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.14 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 57c180

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x1c8(%RDI),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVSXD %ESI,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RBX,%RBX,4),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SAL $0x3,%RBX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 51ed20 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV 0x10(%R13),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
TEST %RAX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 57c1dc <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE6updateEi+0x5c>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV 0x48(%R13),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x90(%R13),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x18(%RDX,%RBX,1),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (,%RAX,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP $0x8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JLE 57c270 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE6updateEi+0xf0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
CALL 4040d0 <memmove@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV 0x10(%R13),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.25
TEST %RAX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 57c224 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE6updateEi+0xa4>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 51ef50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
JNE 57c1dc <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE6updateEi+0x5c>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
VMOVSD (%RSI),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM0,(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
JMP 57c1dc <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE6updateEi+0x5c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
		1	0	1	0	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1
2x2	4	1	1	1.5	0	0.01
2x4	4	1	1	2.25	0	0
2x8	5	1	1	4	0	0
2x16	15	1	1	8.25	0	0
2x32	35	1	1	16.5	0.01	0
2x64	94	1	1	32.5	0.02	0
2x96	167	1	1	48.5	0.03	0

Name	Coverage (%)	Time (s)
▼_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE6updateEi–	0	0
○Loop 2548 - stl_algo.h:731-757 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency