OV - - Function _ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS

	Function: _ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd	Module: exec	Source: OhmmsVector.h:181-301 [...]	Coverage: 0.01%

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/atomic_base.h: 418 - 426

--------------------------------------------------------------------------------

418:       { return __atomic_add_fetch(&_M_i, __i, int(memory_order_seq_cst)); }

[...]

426:       { return __atomic_sub_fetch(&_M_i, __i, int(memory_order_seq_cst)); }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 181 - 301

--------------------------------------------------------------------------------

181:   inline void resize(size_t n, Type_t val = Type_t())

182:   {

183:     static_assert(std::is_same<value_type, typename Alloc::value_type>::value,

184:                   "Vector and Alloc data types must agree!");

185:     if (nLocal > nAllocated)

186:       throw std::runtime_error("Resize not allowed on Vector constructed by initialized memory.");

187:

188:     if (n > nAllocated)

[...]

195:       if (n > nLocal)

196:         qmc_allocator_traits<Alloc>::fill_n(X + nLocal, n - nLocal, val);

197:       nLocal = n;

198:     }

199:     return;

200:   }

[...]

296:     if (nAllocated)

297:     {

298:       mAllocator.deallocate(X, nAllocated);

299:     }

300:     X          = mAllocator.allocate(n);

301:     nLocal     = n;

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algobase.h: 930 - 1128

--------------------------------------------------------------------------------

930:       for (; __first != __last; ++__first)

931: 	*__first = __tmp;

[...]

1128:       std::__fill_a(__first, __first + __n, __value);

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPallocator.hpp: 85 - 112

--------------------------------------------------------------------------------

85:     value_type* pt = HostAllocator::allocate(n);

[...]

93:     device_ptr_ = getOffloadDevicePtr(pt);

94: #endif

95:     OMPallocator_device_mem_allocated += n * sizeof(T);

[...]

101:     OMPallocator_device_mem_allocated -= n * sizeof(T);

[...]

111:     HostAllocator::deallocate(pt, n);

112:   }

0x570c30 PUSH	%RBP

0x570c31 MOV	%RSP,%RBP

0x570c34 PUSH	%R12

0x570c36 PUSH	%RBX

0x570c37 MOV	%RSI,%RBX

0x570c3a AND	$-0x40,%RSP

0x570c3e SUB	$0x40,%RSP

0x570c42 MOV	0x8(%RDI),%RSI

0x570c46 MOV	0x10(%RDI),%RAX

0x570c4a CMP	%RSI,%RAX

0x570c4d JB	571022

0x570c53 MOV	%RDI,%R12

0x570c56 CMP	%RBX,%RAX

0x570c59 JB	570e00

0x570c5f CMP	%RBX,%RSI

0x570c62 JAE	570de3

0x570c68 MOV	0x18(%RDI),%R11

0x570c6c MOV	%RBX,%RDX

0x570c6f SUB	%RSI,%RDX

0x570c72 SAL	$0x3,%RDX

0x570c76 LEA	(%R11,%RSI,8),%RCX

0x570c7a LEA	(%RCX,%RDX,1),%R8

0x570c7e CMP	%R8,%RCX

0x570c81 JE	570de3

0x570c87 SUB	$0x8,%RDX

0x570c8b MOV	%RDX,%RDI

0x570c8e SHR	$0x3,%RDI

0x570c92 LEA	0x1(%RDI),%R9

0x570c96 CMP	$0x30,%RDX

0x570c9a JBE	57100f

0x570ca0 MOV	%R9,%RDX

0x570ca3 VBROADCASTSD	%XMM0,%ZMM1

0x570ca9 MOV	%RCX,%RAX

0x570cac SHR	$0x3,%RDX

0x570cb0 SAL	$0x6,%RDX

0x570cb4 LEA	(%RDX,%RCX,1),%R10

0x570cb8 SUB	$0x40,%RDX

0x570cbc SHR	$0x6,%RDX

0x570cc0 INC	%RDX

0x570cc3 AND	$0x7,%EDX

0x570cc6 JE	570d31

0x570cc8 CMP	$0x1,%RDX

0x570ccc JE	570d22

0x570cce CMP	$0x2,%RDX

0x570cd2 JE	570d18

0x570cd4 CMP	$0x3,%RDX

0x570cd8 JE	570d0e

0x570cda CMP	$0x4,%RDX

0x570cde JE	570d04

0x570ce0 CMP	$0x5,%RDX

0x570ce4 JE	570cfa

0x570ce6 CMP	$0x6,%RDX

0x570cea JNE	570ff0

0x570cf0 VMOVUPD	%ZMM1,(%RAX)

0x570cf6 ADD	$0x40,%RAX

0x570cfa VMOVUPD	%ZMM1,(%RAX)

0x570d00 ADD	$0x40,%RAX

0x570d04 VMOVUPD	%ZMM1,(%RAX)

0x570d0a ADD	$0x40,%RAX

0x570d0e VMOVUPD	%ZMM1,(%RAX)

0x570d14 ADD	$0x40,%RAX

0x570d18 VMOVUPD	%ZMM1,(%RAX)

0x570d1e ADD	$0x40,%RAX

0x570d22 VMOVUPD	%ZMM1,(%RAX)

0x570d28 ADD	$0x40,%RAX

0x570d2c CMP	%RAX,%R10

0x570d2f JE	570d73

(2469) 0x570d31 VMOVUPD	%ZMM1,(%RAX)

(2469) 0x570d37 ADD	$0x200,%RAX

(2469) 0x570d3d VMOVUPD	%ZMM1,-0x1c0(%RAX)

(2469) 0x570d44 VMOVUPD	%ZMM1,-0x180(%RAX)

(2469) 0x570d4b VMOVUPD	%ZMM1,-0x140(%RAX)

(2469) 0x570d52 VMOVUPD	%ZMM1,-0x100(%RAX)

(2469) 0x570d59 VMOVUPD	%ZMM1,-0xc0(%RAX)

(2469) 0x570d60 VMOVUPD	%ZMM1,-0x80(%RAX)

(2469) 0x570d67 VMOVUPD	%ZMM1,-0x40(%RAX)

(2469) 0x570d6e CMP	%RAX,%R10

(2469) 0x570d71 JNE	570d31

0x570d73 MOV	%R9,%R10

0x570d76 AND	$-0x8,%R10

0x570d7a AND	$0x7,%R9D

0x570d7e LEA	(%RCX,%R10,8),%RCX

0x570d82 JE	570fa0

0x570d88 SUB	%R10,%RDI

0x570d8b LEA	0x1(%RDI),%R9

0x570d8f CMP	$0x2,%RDI

0x570d93 JBE	570db8

0x570d95 ADD	%RSI,%R10

0x570d98 MOV	%R9,%RSI

0x570d9b VBROADCASTSD	%XMM0,%YMM2

0x570da0 AND	$-0x4,%RSI

0x570da4 AND	$0x3,%R9D

0x570da8 VMOVUPD	%YMM2,(%R11,%R10,8)

0x570dae LEA	(%RCX,%RSI,8),%RCX

0x570db2 JE	570fa0

0x570db8 LEA	0x8(%RCX),%R11

0x570dbc VMOVSD	%XMM0,(%RCX)

0x570dc0 CMP	%R11,%R8

0x570dc3 JE	570fa0

0x570dc9 LEA	0x10(%RCX),%RDI

0x570dcd VMOVSD	%XMM0,0x8(%RCX)

0x570dd2 CMP	%RDI,%R8

0x570dd5 JE	570fa0

0x570ddb VMOVSD	%XMM0,0x10(%RCX)

0x570de0 VZEROUPPER

0x570de3 MOV	%RBX,0x8(%R12)

0x570de8 LEA	-0x10(%RBP),%RSP

0x570dec POP	%RBX

0x570ded POP	%R12

0x570def POP	%RBP

0x570df0 RET

0x570df1 NOPW	%CS:(%RAX,%RAX,1)

0x570dfc NOPL	(%RAX)

0x570e00 TEST	%RAX,%RAX

0x570e03 JNE	570fc0

0x570e09 MOV	%RBX,%RDI

0x570e0c VMOVSD	%XMM0,0x38(%RSP)

0x570e12 CALL	54f030 <_ZN11qmcplusplus10MallocatorIdLm64EE8allocateEm.isra.0>

0x570e17 LEA	(,%RBX,8),%RDX

0x570e1f MOV	%RAX,%R10

0x570e22 MOV	%RAX,0x20(%R12)

0x570e27 LOCK ADD	%RDX,0x56019(%RIP)

0x570e2f VPBROADCASTQ	%RBX,%XMM0

0x570e35 LEA	(%RAX,%RDX,1),%RBX

0x570e39 MOV	%RAX,0x18(%R12)

0x570e3e VMOVDQU	%XMM0,0x8(%R12)

0x570e45 CMP	%RAX,%RBX

0x570e48 JE	570de8

0x570e4a SUB	$0x8,%RDX

0x570e4e VMOVSD	0x38(%RSP),%XMM3

0x570e54 MOV	%RDX,%R12

0x570e57 SHR	$0x3,%R12

0x570e5b CMP	$0x30,%RDX

0x570e5f LEA	0x1(%R12),%RSI

0x570e64 JBE	571017

0x570e6a MOV	%RSI,%RCX

0x570e6d VBROADCASTSD	%XMM3,%ZMM4

0x570e73 SHR	$0x3,%RCX

0x570e77 SAL	$0x6,%RCX

0x570e7b LEA	(%RCX,%RAX,1),%R11

0x570e7f SUB	$0x40,%RCX

0x570e83 SHR	$0x6,%RCX

0x570e87 INC	%RCX

0x570e8a AND	$0x7,%ECX

0x570e8d JE	570ef8

0x570e8f CMP	$0x1,%RCX

0x570e93 JE	570ee9

0x570e95 CMP	$0x2,%RCX

0x570e99 JE	570edf

0x570e9b CMP	$0x3,%RCX

0x570e9f JE	570ed5

0x570ea1 CMP	$0x4,%RCX

0x570ea5 JE	570ecb

0x570ea7 CMP	$0x5,%RCX

0x570eab JE	570ec1

0x570ead CMP	$0x6,%RCX

0x570eb1 JNE	571000

0x570eb7 VMOVUPD	%ZMM4,(%RAX)

0x570ebd ADD	$0x40,%RAX

0x570ec1 VMOVUPD	%ZMM4,(%RAX)

0x570ec7 ADD	$0x40,%RAX

0x570ecb VMOVUPD	%ZMM4,(%RAX)

0x570ed1 ADD	$0x40,%RAX

0x570ed5 VMOVUPD	%ZMM4,(%RAX)

0x570edb ADD	$0x40,%RAX

0x570edf VMOVUPD	%ZMM4,(%RAX)

0x570ee5 ADD	$0x40,%RAX

0x570ee9 VMOVUPD	%ZMM4,(%RAX)

0x570eef ADD	$0x40,%RAX

0x570ef3 CMP	%R11,%RAX

0x570ef6 JE	570f3a

(2468) 0x570ef8 VMOVUPD	%ZMM4,(%RAX)

(2468) 0x570efe ADD	$0x200,%RAX

(2468) 0x570f04 VMOVUPD	%ZMM4,-0x1c0(%RAX)

(2468) 0x570f0b VMOVUPD	%ZMM4,-0x180(%RAX)

(2468) 0x570f12 VMOVUPD	%ZMM4,-0x140(%RAX)

(2468) 0x570f19 VMOVUPD	%ZMM4,-0x100(%RAX)

(2468) 0x570f20 VMOVUPD	%ZMM4,-0xc0(%RAX)

(2468) 0x570f27 VMOVUPD	%ZMM4,-0x80(%RAX)

(2468) 0x570f2e VMOVUPD	%ZMM4,-0x40(%RAX)

(2468) 0x570f35 CMP	%R11,%RAX

(2468) 0x570f38 JNE	570ef8

0x570f3a MOV	%RSI,%R9

0x570f3d AND	$-0x8,%R9

0x570f41 AND	$0x7,%ESI

0x570f44 LEA	(%R10,%R9,8),%RCX

0x570f48 JE	570fb0

0x570f4a SUB	%R9,%R12

0x570f4d LEA	0x1(%R12),%RDI

0x570f52 CMP	$0x2,%R12

0x570f56 JBE	570f73

0x570f58 MOV	%RDI,%R8

0x570f5b VBROADCASTSD	%XMM3,%YMM5

0x570f60 AND	$-0x4,%R8

0x570f64 AND	$0x3,%EDI

0x570f67 VMOVUPD	%YMM5,(%R10,%R9,8)

0x570f6d LEA	(%RCX,%R8,8),%RCX

0x570f71 JE	570fb0

0x570f73 LEA	0x8(%RCX),%R10

0x570f77 VMOVSD	%XMM3,(%RCX)

0x570f7b CMP	%R10,%RBX

0x570f7e JE	570fb0

0x570f80 LEA	0x10(%RCX),%RDX

0x570f84 VMOVSD	%XMM3,0x8(%RCX)

0x570f89 CMP	%RDX,%RBX

0x570f8c JE	570fb0

0x570f8e VMOVSD	%XMM3,0x10(%RCX)

0x570f93 VZEROUPPER

0x570f96 LEA	-0x10(%RBP),%RSP

0x570f9a POP	%RBX

0x570f9b POP	%R12

0x570f9d POP	%RBP

0x570f9e RET

0x570f9f NOP

0x570fa0 VZEROUPPER

0x570fa3 JMP	570de3

0x570fa8 NOPL	(%RAX,%RAX,1)

0x570fb0 VZEROUPPER

0x570fb3 LEA	-0x10(%RBP),%RSP

0x570fb7 POP	%RBX

0x570fb8 POP	%R12

0x570fba POP	%RBP

0x570fbb RET

0x570fbc NOPL	(%RAX)

0x570fc0 MOV	0x18(%RDI),%RDI

0x570fc4 LEA	(,%RAX,8),%R8

0x570fcc VMOVSD	%XMM0,0x38(%RSP)

0x570fd2 LOCK SUB	%R8,0x55e6e(%RIP)

0x570fda MOV	%RAX,%RSI

0x570fdd CALL	54ec50 <_ZN11qmcplusplus10MallocatorIdLm64EE10deallocateEPdm.isra.0>

0x570fe2 VMOVSD	0x38(%RSP),%XMM0

0x570fe8 JMP	570e09

0x570fed NOPL	(%RAX)

0x570ff0 VMOVUPD	%ZMM1,(%RCX)

0x570ff6 LEA	0x40(%RCX),%RAX

0x570ffa JMP	570cf0

0x570fff NOP

0x571000 VMOVUPD	%ZMM4,(%RAX)

0x571006 LEA	0x40(%RAX),%RAX

0x57100a JMP	570eb7

0x57100f XOR	%R10D,%R10D

0x571012 JMP	570d88

0x571017 MOV	%RAX,%RCX

0x57101a XOR	%R9D,%R9D

0x57101d JMP	570f4a

0x571022 MOV	$0x10,%EDI

0x571027 CALL	4044b0 <__cxa_allocate_exception@plt>

0x57102c MOV	$0x5a33d8,%ESI

0x571031 MOV	%RAX,%RDI

0x571034 MOV	%RAX,%RBX

0x571037 CALL	404110 <_ZNSt13runtime_errorC1EPKc@plt>

0x57103c MOV	$0x4046e0,%EDX

0x571041 MOV	$0x5c5b80,%ESI

0x571046 MOV	%RBX,%RDI

0x571049 CALL	404200 <__cxa_throw@plt>

0x57104e MOV	%RAX,%R12

0x571051 MOV	%RBX,%RDI

0x571054 VZEROUPPER

0x571057 CALL	404720 <__cxa_free_exception@plt>

0x57105c MOV	%R12,%RDI

0x57105f CALL	404230 <_Unwind_Resume@plt>

0x571064 NOPW	%CS:(%RAX,%RAX,1)

0x57106e XCHG	%AX,%AX

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	OhmmsVector.h:181-301
Module	exec

The function is defined in:

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/atomic_base.h:418,426
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:181-188,195-200,296-301
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algobase.h:930-931,1128
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPallocator.hpp:85,93-95,101,111-112

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 42.67 to 19.50 cycles (2.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 32% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 42.67 to 34.41 cycles (1.24x speedup).

Details

31% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
58% of SSE/AVX stores are used in vector version.
13% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_Unwind_Resume@plt: 1 occurrences
_ZN11qmcplusplus10MallocatorIdLm64EE10deallocateEPdm.isra.0: 1 occurrences
_ZN11qmcplusplus10MallocatorIdLm64EE8allocateEm.isra.0: 1 occurrences
_ZNSt13runtime_errorC1EPKc@plt: 1 occurrences
__cxa_allocate_exception@plt: 1 occurrences
__cxa_free_exception@plt: 1 occurrences
__cxa_throw@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 1 occurrences
SUB: 1 occurrences
VMOVUPD: 14 occurrences
VPBROADCASTQ: 1 occurrences

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 1080 bytes.

General properties

nb instructions	241
nb uops	256
loop length	956
used x86 registers	13
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	2
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	42.67 cycles
front end	42.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	31.50	31.50	31.50	31.50	25.00	14.33	14.33	14.33	0.00	2.50	2.50	0.00	19.50	19.50
cycles	31.50	31.50	31.50	31.50	25.00	14.33	14.33	14.33	0.00	2.50	2.50	0.00	19.50	19.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	42.67
Dispatch	31.50
Overall L1	42.67

Vectorization ratios

INT

all	15%
load	0%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	53%
load	0%
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	31%
load	0%
store	58%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Vector efficiency ratios

INT

all	14%
load	12%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	55%
load	12%
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	32%
load	12%
store	57%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 42.67 cycles. At this rate:

1% of peak load performance is reached (1.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
39% of peak store performance is reached (25.31 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 42.67 to 31.50 cycles (1.35x speedup).

ASM code

In the binary file, the address of the function is: 570c30

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SUB $0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV 0x8(%RDI),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x10(%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CMP %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JB 571022 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x3f2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JB 570e00 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x1d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP %RBX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JAE 570de3 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x1b3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV 0x18(%RDI),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SAL $0x3,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LEA (%R11,%RSI,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA (%RCX,%RDX,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570de3 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x1b3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
SUB $0x8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LEA 0x1(%RDI),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $0x30,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JBE 57100f <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x3df>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %R9,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VBROADCASTSD %XMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SAL $0x6,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LEA (%RDX,%RCX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SUB $0x40,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SHR $0x6,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
AND $0x7,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570d31 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x101>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570d22 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0xf2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570d18 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0xe8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x3,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570d0e <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0xde>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x4,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570d04 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0xd4>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x5,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570cfa <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0xca>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x6,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 570ff0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x3c0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
VMOVUPD %ZMM1,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM1,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM1,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM1,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM1,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM1,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %RAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570d73 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x143>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
AND $0x7,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA (%RCX,%R10,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570fa0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x370>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
SUB %R10,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%RDI),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $0x2,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JBE 570db8 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
ADD %RSI,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VBROADCASTSD %XMM0,%YMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
AND $-0x4,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
AND $0x3,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %YMM2,(%R11,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
LEA (%RCX,%RSI,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570fa0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x370>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA 0x8(%RCX),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %R11,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570fa0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x370>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA 0x10(%RCX),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %RDI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570fa0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x370>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
VMOVSD %XMM0,0x10(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1
MOV %RBX,0x8(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
LEA -0x10(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
TEST %RAX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 570fc0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x390>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD %XMM0,0x38(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CALL 54f030 <_ZN11qmcplusplus10MallocatorIdLm64EE8allocateEm.isra.0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
LEA (,%RBX,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,0x20(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
LOCK ADD %RDX,0x56019(%RIP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VPBROADCASTQ %RBX,%XMM0	2	0	0	0	0	0	0	0	0	1	0	0	0	1	1
LEA (%RAX,%RDX,1),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RAX,0x18(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
VMOVDQU %XMM0,0x8(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
CMP %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570de8 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x1b8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
SUB $0x8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD 0x38(%RSP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%R12	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP $0x30,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%R12),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JBE 571017 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x3e7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VBROADCASTSD %XMM3,%ZMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	1
SHR $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SAL $0x6,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LEA (%RCX,%RAX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SUB $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SHR $0x6,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INC %RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
AND $0x7,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570ef8 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x2c8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570ee9 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x2b9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x2,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570edf <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x2af>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x3,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570ed5 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x2a5>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x4,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570ecb <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x29b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x5,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570ec1 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x291>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x6,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 571000 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x3d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
VMOVUPD %ZMM4,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM4,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM4,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM4,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM4,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM4,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R11,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570f3a <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x30a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
AND $0x7,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA (%R10,%R9,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570fb0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x380>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
SUB %R9,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%R12),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $0x2,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JBE 570f73 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x343>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VBROADCASTSD %XMM3,%YMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
AND $-0x4,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
AND $0x3,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %YMM5,(%R10,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
LEA (%RCX,%R8,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570fb0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x380>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA 0x8(%RCX),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM3,(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %R10,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570fb0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x380>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA 0x10(%RCX),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM3,0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %RDX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570fb0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x380>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
VMOVSD %XMM3,0x10(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1
LEA -0x10(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1
JMP 570de3 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x1b3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1
LEA -0x10(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0x18(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
LEA (,%RAX,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,0x38(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
LOCK SUB %R8,0x55e6e(%RIP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 54ec50 <_ZN11qmcplusplus10MallocatorIdLm64EE10deallocateEPdm.isra.0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
VMOVSD 0x38(%RSP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
JMP 570e09 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x1d9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VMOVUPD %ZMM1,(%RCX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
LEA 0x40(%RCX),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JMP 570cf0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0xc0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VMOVUPD %ZMM4,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
LEA 0x40(%RAX),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JMP 570eb7 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x287>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 570d88 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x158>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 570f4a <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x31a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
MOV $0x10,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CALL 4044b0 <__cxa_allocate_exception@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV $0x5a33d8,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV $0x4046e0,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV $0x5c5b80,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 404200 <__cxa_throw@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1
CALL 404720 <__cxa_free_exception@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 404230 <_Unwind_Resume@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	OhmmsVector.h:181-301
Module	exec

The function is defined in:

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/atomic_base.h:418,426
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:181-188,195-200,296-301
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_algobase.h:930-931,1128
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPallocator.hpp:85,93-95,101,111-112

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

31% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
58% of SSE/AVX stores are used in vector version.
13% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

_Unwind_Resume@plt: 1 occurrences
_ZN11qmcplusplus10MallocatorIdLm64EE10deallocateEPdm.isra.0: 1 occurrences
_ZN11qmcplusplus10MallocatorIdLm64EE8allocateEm.isra.0: 1 occurrences
_ZNSt13runtime_errorC1EPKc@plt: 1 occurrences
__cxa_allocate_exception@plt: 1 occurrences
__cxa_free_exception@plt: 1 occurrences
__cxa_throw@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 1 occurrences
SUB: 1 occurrences
VMOVUPD: 14 occurrences
VPBROADCASTQ: 1 occurrences

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 1080 bytes.

General properties

nb instructions	241
nb uops	256
loop length	956
used x86 registers	13
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	2
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	42.67 cycles
front end	42.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	31.50	31.50	31.50	31.50	25.00	14.33	14.33	14.33	0.00	2.50	2.50	0.00	19.50	19.50
cycles	31.50	31.50	31.50	31.50	25.00	14.33	14.33	14.33	0.00	2.50	2.50	0.00	19.50	19.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	42.67
Dispatch	31.50
Overall L1	42.67

Vectorization ratios

INT

all	15%
load	0%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	53%
load	0%
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	31%
load	0%
store	58%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Vector efficiency ratios

INT

all	14%
load	12%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	55%
load	12%
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	32%
load	12%
store	57%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 42.67 cycles. At this rate:

1% of peak load performance is reached (1.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
39% of peak store performance is reached (25.31 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 570c30

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SUB $0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV 0x8(%RDI),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x10(%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CMP %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JB 571022 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x3f2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JB 570e00 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x1d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP %RBX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JAE 570de3 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x1b3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV 0x18(%RDI),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SAL $0x3,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LEA (%R11,%RSI,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA (%RCX,%RDX,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570de3 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x1b3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
SUB $0x8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LEA 0x1(%RDI),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $0x30,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JBE 57100f <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x3df>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %R9,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VBROADCASTSD %XMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SAL $0x6,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LEA (%RDX,%RCX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SUB $0x40,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SHR $0x6,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
AND $0x7,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570d31 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x101>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570d22 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0xf2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570d18 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0xe8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x3,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570d0e <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0xde>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x4,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570d04 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0xd4>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x5,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570cfa <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0xca>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x6,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 570ff0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x3c0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
VMOVUPD %ZMM1,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM1,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM1,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM1,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM1,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM1,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %RAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570d73 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x143>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
AND $0x7,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA (%RCX,%R10,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570fa0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x370>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
SUB %R10,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%RDI),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $0x2,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JBE 570db8 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
ADD %RSI,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VBROADCASTSD %XMM0,%YMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
AND $-0x4,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
AND $0x3,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %YMM2,(%R11,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
LEA (%RCX,%RSI,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570fa0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x370>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA 0x8(%RCX),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %R11,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570fa0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x370>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA 0x10(%RCX),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %RDI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570fa0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x370>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
VMOVSD %XMM0,0x10(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1
MOV %RBX,0x8(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
LEA -0x10(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
TEST %RAX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 570fc0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x390>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD %XMM0,0x38(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CALL 54f030 <_ZN11qmcplusplus10MallocatorIdLm64EE8allocateEm.isra.0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
LEA (,%RBX,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,0x20(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
LOCK ADD %RDX,0x56019(%RIP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VPBROADCASTQ %RBX,%XMM0	2	0	0	0	0	0	0	0	0	1	0	0	0	1	1
LEA (%RAX,%RDX,1),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RAX,0x18(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
VMOVDQU %XMM0,0x8(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
CMP %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570de8 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x1b8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
SUB $0x8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD 0x38(%RSP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%R12	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP $0x30,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%R12),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JBE 571017 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x3e7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VBROADCASTSD %XMM3,%ZMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	1
SHR $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SAL $0x6,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LEA (%RCX,%RAX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SUB $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SHR $0x6,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INC %RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
AND $0x7,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570ef8 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x2c8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570ee9 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x2b9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x2,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570edf <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x2af>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x3,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570ed5 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x2a5>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x4,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570ecb <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x29b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x5,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570ec1 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x291>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x6,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 571000 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x3d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
VMOVUPD %ZMM4,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM4,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM4,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM4,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM4,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %ZMM4,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x40,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R11,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570f3a <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x30a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
AND $0x7,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA (%R10,%R9,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570fb0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x380>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
SUB %R9,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%R12),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $0x2,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JBE 570f73 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x343>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VBROADCASTSD %XMM3,%YMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
AND $-0x4,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
AND $0x3,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %YMM5,(%R10,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
LEA (%RCX,%R8,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570fb0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x380>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA 0x8(%RCX),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM3,(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %R10,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570fb0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x380>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA 0x10(%RCX),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM3,0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %RDX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 570fb0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x380>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
VMOVSD %XMM3,0x10(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1
LEA -0x10(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1
JMP 570de3 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x1b3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1
LEA -0x10(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0x18(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
LEA (,%RAX,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,0x38(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
LOCK SUB %R8,0x55e6e(%RIP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 54ec50 <_ZN11qmcplusplus10MallocatorIdLm64EE10deallocateEPdm.isra.0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
VMOVSD 0x38(%RSP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
JMP 570e09 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x1d9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VMOVUPD %ZMM1,(%RCX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
LEA 0x40(%RCX),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JMP 570cf0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0xc0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VMOVUPD %ZMM4,(%RAX)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
LEA 0x40(%RAX),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JMP 570eb7 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x287>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 570d88 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x158>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 570f4a <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd+0x31a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
MOV $0x10,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CALL 4044b0 <__cxa_allocate_exception@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV $0x5a33d8,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 404110 <_ZNSt13runtime_errorC1EPKc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV $0x4046e0,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV $0x5c5b80,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 404200 <__cxa_throw@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1
CALL 404720 <__cxa_free_exception@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 404230 <_Unwind_Resume@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	1	0	1	0	1	0	0	0	0	0	0	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0	0.01
2x2	4	1	1	1.5	0	0
2x4	8	1	1	2.25	0	0
2x8	16	1	1	4	0.01	0.01
2x16	32	1	1	8.25	0.02	0.01
2x32	64	0	0	16.5	0.03	0
2x64	128	0	0	32.5	0.05	0
2x96	192	0	0	48.5	0.05	0

Name	Coverage (%)	Time (s)
▼_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm64EEEEEE6resizeEmd–	0.01	0
○Loop 2468 - stl_algobase.h:930-931 - exec	0.01	0
○Loop 2469 - stl_algobase.h:930-931 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency