OV - - Loop 896

	Loop Id: 896	Module: exec	Source: MultiBsplineRef.hpp:227-262	Coverage: 0.02%

0x482079 MOV	0xd0(%RSP),%R13

0x482081 MOV	%R9,%RSI

0x482084 MOV	0xe0(%RSP),%RAX

0x48208c MOV	%RDX,%RDI

0x48208f MOV	0xc8(%RSP),%RDX

0x482097 MOV	%RCX,0xd8(%RSP)

0x48209f SUB	%R13,%RSI

0x4820a2 MOV	%R9,%R13

0x4820a5 VMOVSD	0x120(%RSP,%RAX,1),%XMM4

0x4820ae VMOVSD	0x160(%RSP,%RAX,1),%XMM5

0x4820b7 MOV	%RSI,%R9

0x4820ba MOV	0xc0(%RSP),%RSI

0x4820c2 VMULSD	0x1a0(%RSP,%RAX,1),%XMM22,%XMM31

0x4820ca XOR	%EAX,%EAX

0x4820cc VMULSD	%XMM4,%XMM24,%XMM9

0x4820d2 VMULSD	%XMM23,%XMM4,%XMM29

0x4820d8 VMULSD	%XMM5,%XMM23,%XMM30

0x4820de VMULSD	%XMM22,%XMM4,%XMM4

0x4820e4 VMULSD	%XMM5,%XMM22,%XMM5

0x4820ea NOPW	(%RAX,%RAX,1)

  (895) 0x4820f0 VMOVSD	(%R9,%RAX,8),%XMM2

  (895) 0x4820f6 VMOVSD	(%R13,%RAX,8),%XMM26

  (895) 0x4820fe VMOVSD	(%RDI,%RAX,8),%XMM3

  (895) 0x482103 VMOVSD	(%R10,%RAX,8),%XMM25

  (895) 0x48210a VMULSD	%XMM11,%XMM26,%XMM0

  (895) 0x482110 VMULSD	%XMM13,%XMM25,%XMM1

  (895) 0x482116 VFMADD231SD	%XMM16,%XMM2,%XMM0

  (895) 0x48211c VFMADD231SD	%XMM12,%XMM3,%XMM1

  (895) 0x482121 MOV	0xf8(%RSP),%RCX

  (895) 0x482129 VMULSD	%XMM19,%XMM25,%XMM27

  (895) 0x48212f VMULSD	%XMM10,%XMM25,%XMM25

  (895) 0x482135 VFMADD231SD	%XMM14,%XMM3,%XMM27

  (895) 0x48213b VFMADD132SD	%XMM17,%XMM25,%XMM3

  (895) 0x482141 VADDSD	%XMM1,%XMM0,%XMM0

  (895) 0x482145 VMULSD	%XMM21,%XMM26,%XMM1

  (895) 0x48214b VMULSD	%XMM20,%XMM26,%XMM26

  (895) 0x482151 VFMADD231SD	%XMM18,%XMM2,%XMM1

  (895) 0x482157 VFMADD132SD	%XMM15,%XMM26,%XMM2

  (895) 0x48215d VADDSD	%XMM27,%XMM1,%XMM1

  (895) 0x482163 VADDSD	%XMM3,%XMM2,%XMM2

  (895) 0x482167 VMOVSD	%XMM9,%XMM9,%XMM3

  (895) 0x48216b VFMADD213SD	(%R11,%RAX,8),%XMM0,%XMM3

  (895) 0x482171 VMOVSD	%XMM3,(%R11,%RAX,8)

  (895) 0x482177 VMOVSD	%XMM30,%XMM30,%XMM3

  (895) 0x48217d VFMADD213SD	(%R14,%RAX,8),%XMM0,%XMM3

  (895) 0x482183 VMOVSD	%XMM3,(%R14,%RAX,8)

  (895) 0x482189 VMOVSD	%XMM29,%XMM29,%XMM3

  (895) 0x48218f VFMADD213SD	(%R15,%RAX,8),%XMM1,%XMM3

  (895) 0x482195 VMOVSD	%XMM3,(%R15,%RAX,8)

  (895) 0x48219b VMOVSD	%XMM31,%XMM31,%XMM3

  (895) 0x4821a1 VFMADD213SD	(%RDX,%RAX,8),%XMM0,%XMM3

  (895) 0x4821a7 VMOVSD	%XMM3,(%RDX,%RAX,8)

  (895) 0x4821ac VMOVSD	%XMM5,%XMM5,%XMM3

  (895) 0x4821b0 VFMADD213SD	(%RSI,%RAX,8),%XMM1,%XMM3

  (895) 0x4821b6 VMOVSD	%XMM3,(%RSI,%RAX,8)

  (895) 0x4821bb VMOVSD	%XMM5,%XMM5,%XMM3

  (895) 0x4821bf VFMADD213SD	(%RBX,%RAX,8),%XMM4,%XMM2

  (895) 0x4821c5 VMOVSD	%XMM2,(%RBX,%RAX,8)

  (895) 0x4821ca VMOVSD	%XMM29,%XMM29,%XMM2

  (895) 0x4821d0 VFMADD213SD	(%R12,%RAX,8),%XMM0,%XMM2

  (895) 0x4821d6 VMOVSD	%XMM2,(%R12,%RAX,8)

  (895) 0x4821dc VFMADD213SD	(%R8,%RAX,8),%XMM0,%XMM3

  (895) 0x4821e2 VMOVSD	%XMM3,(%R8,%RAX,8)

  (895) 0x4821e8 VFMADD213SD	(%RCX,%RAX,8),%XMM4,%XMM1

  (895) 0x4821ee VMOVSD	%XMM1,(%RCX,%RAX,8)

  (895) 0x4821f3 MOV	0xf0(%RSP),%RCX

  (895) 0x4821fb VFMADD213SD	(%RCX,%RAX,8),%XMM4,%XMM0

  (895) 0x482201 VMOVSD	%XMM0,(%RCX,%RAX,8)

  (895) 0x482206 MOV	%RAX,%RCX

  (895) 0x482209 INC	%RAX

  (895) 0x48220c CMP	%RCX,0xe8(%RSP)

  (895) 0x482214 JNE	4820f0

0x48221a MOV	0xd8(%RSP),%RCX

0x482222 ADDQ	$0x8,0xe0(%RSP)

0x48222b MOV	0xe0(%RSP),%RAX

0x482233 MOV	%RDI,%RDX

0x482236 MOV	%R13,%R9

0x482239 ADD	%RCX,%R9

0x48223c ADD	%RCX,%RDX

0x48223f ADD	%RCX,%R10

0x482242 CMP	$0x20,%RAX

0x482246 JNE	482079

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 227 - 262

--------------------------------------------------------------------------------

227:     for (int j = 0; j < 4; j++)

228:     {

229:       const T* restrict coefs    = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs;

230:       const T* restrict coefszs  = coefs + zs;

231:       const T* restrict coefs2zs = coefs + 2 * zs;

232:       const T* restrict coefs3zs = coefs + 3 * zs;

233:

234:       const T pre20 = d2a[i] * b[j];

235:       const T pre10 = da[i] * b[j];

236:       const T pre00 = a[i] * b[j];

237:       const T pre11 = da[i] * db[j];

238:       const T pre01 = a[i] * db[j];

239:       const T pre02 = a[i] * d2b[j];

240:

241:       const int iSplitPoint = num_splines;

242:       for (int n = 0; n < iSplitPoint; n++)

243:       {

244:         T coefsv    = coefs[n];

245:         T coefsvzs  = coefszs[n];

246:         T coefsv2zs = coefs2zs[n];

247:         T coefsv3zs = coefs3zs[n];

248:

249:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

250:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

251:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

252:

253:         hxx[n] += pre20 * sum0;

254:         hxy[n] += pre11 * sum0;

255:         hxz[n] += pre10 * sum1;

256:         hyy[n] += pre02 * sum0;

257:         hyz[n] += pre01 * sum1;

258:         hzz[n] += pre00 * sum2;

259:         gx[n] += pre10 * sum0;

260:         gy[n] += pre01 * sum0;

261:         gz[n] += pre00 * sum1;

262:         vals[n] += pre00 * sum0;

Path /

Metric	Value
CQA speedup if no scalar integer	1.61
CQA speedup if FP arith vectorized	1.53
CQA speedup if fully vectorized	5.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	micro-operation queue,
Function	_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m
Source	MultiBsplineRef.hpp:227-229,MultiBsplineRef.hpp:234-239,MultiBsplineRef.hpp:242-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.83
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.17
CQA cycles if fully vectorized	0.83
Front-end cycles	4.83
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	0.50
P4 cycles	3.67
P5 cycles	3.67
P6 cycles	3.67
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	29.00
Nb loads	10.00
Nb stores	2.00
Nb stack references	5.00
FLOP/cycle	1.24
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.86
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	16.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	14.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.61
CQA speedup if FP arith vectorized	1.53
CQA speedup if fully vectorized	5.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	micro-operation queue,
Function	_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m
Source	MultiBsplineRef.hpp:227-229,MultiBsplineRef.hpp:234-239,MultiBsplineRef.hpp:242-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.83
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.17
CQA cycles if fully vectorized	0.83
Front-end cycles	4.83
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	0.50
P4 cycles	3.67
P5 cycles	3.67
P6 cycles	3.67
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	29.00
Nb loads	10.00
Nb stores	2.00
Nb stack references	5.00
FLOP/cycle	1.24
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.86
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	16.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	14.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m
Source file and lines	MultiBsplineRef.hpp:227-262
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:227-262.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:227-229,234-239,242.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.83 to 3.00 cycles (1.61x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 4.83 to 0.83 cycles (5.80x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 14 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

6: multiply

The binary loop is loading 80 bytes (10 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	30
nb uops	29
loop length	169
used x86 registers	9
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.83 cycles
front end	4.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.50	1.50	1.25	1.25	0.50	3.67	3.67	3.67	3.00	3.00	0.00	0.00	0.00	0.00
cycles	1.50	1.50	1.25	1.25	0.50	3.67	3.67	3.67	3.00	3.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.83
Dispatch	3.67
Data deps.	1.00
Overall L1	4.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.83 cycles. At this rate:

17% of peak load performance is reached (16.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.31 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.83 to 3.67 cycles (1.32x speedup).

ASM code

In the binary file, the address of the loop is: 482079

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	Latency	Recip. throughput
MOV 0xd0(%RSP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xe0(%RSP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc8(%RSP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RCX,0xd8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
SUB %R13,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD 0x120(%RSP,%RAX,1),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD 0x160(%RSP,%RAX,1),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc0(%RSP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMULSD 0x1a0(%RSP,%RAX,1),%XMM22,%XMM31	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	0.50
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
VMULSD %XMM4,%XMM24,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
VMULSD %XMM23,%XMM4,%XMM29	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
VMULSD %XMM5,%XMM23,%XMM30	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
VMULSD %XMM22,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
VMULSD %XMM5,%XMM22,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0xd8(%RSP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADDQ $0x8,0xe0(%RSP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.50
MOV 0xe0(%RSP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R13,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD %RCX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RCX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP $0x20,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 482079 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x769>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m
Source file and lines	MultiBsplineRef.hpp:227-262
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.83 to 3.00 cycles (1.61x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 4.83 to 0.83 cycles (5.80x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 14 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

6: multiply

The binary loop is loading 80 bytes (10 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	30
nb uops	29
loop length	169
used x86 registers	9
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.83 cycles
front end	4.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.50	1.50	1.25	1.25	0.50	3.67	3.67	3.67	3.00	3.00	0.00	0.00	0.00	0.00
cycles	1.50	1.50	1.25	1.25	0.50	3.67	3.67	3.67	3.00	3.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.83
Dispatch	3.67
Data deps.	1.00
Overall L1	4.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.83 cycles. At this rate:

17% of peak load performance is reached (16.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.31 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 482079

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	Latency	Recip. throughput
MOV 0xd0(%RSP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xe0(%RSP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc8(%RSP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RCX,0xd8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
SUB %R13,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD 0x120(%RSP,%RAX,1),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD 0x160(%RSP,%RAX,1),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc0(%RSP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMULSD 0x1a0(%RSP,%RAX,1),%XMM22,%XMM31	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	3	0.50
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
VMULSD %XMM4,%XMM24,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
VMULSD %XMM23,%XMM4,%XMM29	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
VMULSD %XMM5,%XMM23,%XMM30	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
VMULSD %XMM22,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
VMULSD %XMM5,%XMM22,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0xd8(%RSP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADDQ $0x8,0xe0(%RSP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.50
MOV 0xe0(%RSP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R13,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD %RCX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RCX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP $0x20,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 482079 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x769>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.6	0	1	0	0.18	0.02	0.09	0.01	0.05	0.01	0.02	0.01	0.01	0.01

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.01	0.02
2x2	4	0.6	1	1.6666666666667	0.02	0.01
2x4	8	1	1	3.3333333333333	0.01	0.01
2x8	16	0.18	1	5.6666666666667	0.02	0.02
2x16	32	0.09	1	11.333333333333	0.01	0.01
2x32	64	0.05	1	22	0.02	0.01
2x64	128	0.02	1	43.333333333333	0.02	0.01
2x96	192	0.01	0.5	64.666666666667	0.04	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency