OV - - Loop 895

	Loop Id: 895	Module: exec	Source: MultiBsplineRef.hpp:242-262	Coverage: 19.83%

0x4820f0 VMOVSD	(%R9,%RAX,8),%XMM2    [8]

0x4820f6 VMOVSD	(%R13,%RAX,8),%XMM26    [9]

0x4820fe VMOVSD	(%RDI,%RAX,8),%XMM3    [15]

0x482103 VMOVSD	(%R10,%RAX,8),%XMM25    [12]

0x48210a VMULSD	%XMM11,%XMM26,%XMM0

0x482110 VMULSD	%XMM13,%XMM25,%XMM1

0x482116 VFMADD231SD	%XMM16,%XMM2,%XMM0

0x48211c VFMADD231SD	%XMM12,%XMM3,%XMM1

0x482121 MOV	0xf8(%RSP),%RCX    [14]

0x482129 VMULSD	%XMM19,%XMM25,%XMM27

0x48212f VMULSD	%XMM10,%XMM25,%XMM25

0x482135 VFMADD231SD	%XMM14,%XMM3,%XMM27

0x48213b VFMADD132SD	%XMM17,%XMM25,%XMM3

0x482141 VADDSD	%XMM1,%XMM0,%XMM0

0x482145 VMULSD	%XMM21,%XMM26,%XMM1

0x48214b VMULSD	%XMM20,%XMM26,%XMM26

0x482151 VFMADD231SD	%XMM18,%XMM2,%XMM1

0x482157 VFMADD132SD	%XMM15,%XMM26,%XMM2

0x48215d VADDSD	%XMM27,%XMM1,%XMM1

0x482163 VADDSD	%XMM3,%XMM2,%XMM2

0x482167 VMOVSD	%XMM9,%XMM9,%XMM3

0x48216b VFMADD213SD	(%R11,%RAX,8),%XMM0,%XMM3    [10]

0x482171 VMOVSD	%XMM3,(%R11,%RAX,8)    [10]

0x482177 VMOVSD	%XMM30,%XMM30,%XMM3

0x48217d VFMADD213SD	(%R14,%RAX,8),%XMM0,%XMM3    [7]

0x482183 VMOVSD	%XMM3,(%R14,%RAX,8)    [7]

0x482189 VMOVSD	%XMM29,%XMM29,%XMM3

0x48218f VFMADD213SD	(%R15,%RAX,8),%XMM1,%XMM3    [3]

0x482195 VMOVSD	%XMM3,(%R15,%RAX,8)    [3]

0x48219b VMOVSD	%XMM31,%XMM31,%XMM3

0x4821a1 VFMADD213SD	(%RDX,%RAX,8),%XMM0,%XMM3    [11]

0x4821a7 VMOVSD	%XMM3,(%RDX,%RAX,8)    [11]

0x4821ac VMOVSD	%XMM5,%XMM5,%XMM3

0x4821b0 VFMADD213SD	(%RSI,%RAX,8),%XMM1,%XMM3    [5]

0x4821b6 VMOVSD	%XMM3,(%RSI,%RAX,8)    [5]

0x4821bb VMOVSD	%XMM5,%XMM5,%XMM3

0x4821bf VFMADD213SD	(%RBX,%RAX,8),%XMM4,%XMM2    [6]

0x4821c5 VMOVSD	%XMM2,(%RBX,%RAX,8)    [6]

0x4821ca VMOVSD	%XMM29,%XMM29,%XMM2

0x4821d0 VFMADD213SD	(%R12,%RAX,8),%XMM0,%XMM2    [13]

0x4821d6 VMOVSD	%XMM2,(%R12,%RAX,8)    [13]

0x4821dc VFMADD213SD	(%R8,%RAX,8),%XMM0,%XMM3    [2]

0x4821e2 VMOVSD	%XMM3,(%R8,%RAX,8)    [2]

0x4821e8 VFMADD213SD	(%RCX,%RAX,8),%XMM4,%XMM1    [4]

0x4821ee VMOVSD	%XMM1,(%RCX,%RAX,8)    [4]

0x4821f3 MOV	0xf0(%RSP),%RCX    [14]

0x4821fb VFMADD213SD	(%RCX,%RAX,8),%XMM4,%XMM0    [1]

0x482201 VMOVSD	%XMM0,(%RCX,%RAX,8)    [1]

0x482206 MOV	%RAX,%RCX

0x482209 INC	%RAX

0x48220c CMP	%RCX,0xe8(%RSP)    [14]

0x482214 JNE	4820f0

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 242 - 262

--------------------------------------------------------------------------------

242:       for (int n = 0; n < iSplitPoint; n++)

243:       {

244:         T coefsv    = coefs[n];

245:         T coefsvzs  = coefszs[n];

246:         T coefsv2zs = coefs2zs[n];

247:         T coefsv3zs = coefs3zs[n];

248:

249:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

250:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

251:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

252:

253:         hxx[n] += pre20 * sum0;

254:         hxy[n] += pre11 * sum0;

255:         hxz[n] += pre10 * sum1;

256:         hyy[n] += pre02 * sum0;

257:         hyz[n] += pre01 * sum1;

258:         hzz[n] += pre00 * sum2;

259:         gx[n] += pre10 * sum0;

260:         gy[n] += pre01 * sum0;

261:         gz[n] += pre00 * sum1;

262:         vals[n] += pre00 * sum0;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.33
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.22
Bottlenecks	P8, P9,
Function	_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m
Source	MultiBsplineRef.hpp:242-262
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	8.25
CQA cycles if fully vectorized	2.75
Front-end cycles	8.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	9.00
P5 cycles	9.00
P6 cycles	9.00
P7 cycles	11.00
P8 cycles	11.00
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	5.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	51.00
Nb loads	17.00
Nb stores	10.00
Nb stack references	3.00
FLOP/cycle	3.73
Nb FLOP add-sub	3.00
Nb FLOP mul	6.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.64
Bytes prefetched	0.00
Bytes loaded	136.00
Bytes stored	80.00
Stride 0	1.00
Stride 1	12.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.33
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.22
Bottlenecks	P8, P9,
Function	_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m
Source	MultiBsplineRef.hpp:242-262
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	8.25
CQA cycles if fully vectorized	2.75
Front-end cycles	8.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	9.00
P5 cycles	9.00
P6 cycles	9.00
P7 cycles	11.00
P8 cycles	11.00
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	5.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	51.00
Nb loads	17.00
Nb stores	10.00
Nb stack references	3.00
FLOP/cycle	3.73
Nb FLOP add-sub	3.00
Nb FLOP mul	6.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.64
Bytes prefetched	0.00
Bytes loaded	136.00
Bytes stored	80.00
Stride 0	1.00
Stride 1	12.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m
Source file and lines	MultiBsplineRef.hpp:242-262
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:242-262.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 11.00 to 2.75 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.00 to 9.00 cycles (1.22x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

25 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 41 FP arithmetical operations:

19: addition or subtraction (16 inside FMA instructions)
22: multiply (16 inside FMA instructions)

The binary loop is loading 136 bytes (17 double precision FP elements). The binary loop is storing 80 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	52
nb uops	51
loop length	298
used x86 registers	15
used mmx registers	0
used xmm registers	25
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	0.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	9.00	9.00	9.00	11.00	11.00	5.00	5.00	5.00	5.00
cycles	0.50	0.50	0.25	0.25	0.50	9.00	9.00	9.00	11.00	11.00	5.00	5.00	5.00	5.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.50
Dispatch	11.00
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

12% of peak load performance is reached (12.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.27 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4820f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVSD (%R9,%RAX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%R13,%RAX,8),%XMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RDI,%RAX,8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%R10,%RAX,8),%XMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMULSD %XMM11,%XMM26,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM13,%XMM25,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM16,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM12,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOV 0xf8(%RSP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMULSD %XMM19,%XMM25,%XMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM10,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM14,%XMM3,%XMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD132SD %XMM17,%XMM25,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM21,%XMM26,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM20,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM18,%XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD132SD %XMM15,%XMM26,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VADDSD %XMM27,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM3,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD %XMM9,%XMM9,%XMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD213SD (%R11,%RAX,8),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM3,(%R11,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM30,%XMM30,%XMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD213SD (%R14,%RAX,8),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM3,(%R14,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM29,%XMM29,%XMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD213SD (%R15,%RAX,8),%XMM1,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM3,(%R15,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM31,%XMM31,%XMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD213SD (%RDX,%RAX,8),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM3,(%RDX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM5,%XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD213SD (%RSI,%RAX,8),%XMM1,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM3,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM5,%XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD213SD (%RBX,%RAX,8),%XMM4,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM2,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM29,%XMM29,%XMM2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD213SD (%R12,%RAX,8),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM2,(%R12,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMADD213SD (%R8,%RAX,8),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM3,(%R8,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMADD213SD (%RCX,%RAX,8),%XMM4,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM1,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0xf0(%RSP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VFMADD213SD (%RCX,%RAX,8),%XMM4,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RCX,0xe8(%RSP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JNE 4820f0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x7e0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m
Source file and lines	MultiBsplineRef.hpp:242-262
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 11.00 to 2.75 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

25 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 41 FP arithmetical operations:

19: addition or subtraction (16 inside FMA instructions)
22: multiply (16 inside FMA instructions)

The binary loop is loading 136 bytes (17 double precision FP elements). The binary loop is storing 80 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	52
nb uops	51
loop length	298
used x86 registers	15
used mmx registers	0
used xmm registers	25
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	0.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	9.00	9.00	9.00	11.00	11.00	5.00	5.00	5.00	5.00
cycles	0.50	0.50	0.25	0.25	0.50	9.00	9.00	9.00	11.00	11.00	5.00	5.00	5.00	5.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.50
Dispatch	11.00
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

12% of peak load performance is reached (12.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.27 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4820f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVSD (%R9,%RAX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%R13,%RAX,8),%XMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RDI,%RAX,8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%R10,%RAX,8),%XMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMULSD %XMM11,%XMM26,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM13,%XMM25,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM16,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM12,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOV 0xf8(%RSP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMULSD %XMM19,%XMM25,%XMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM10,%XMM25,%XMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM14,%XMM3,%XMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD132SD %XMM17,%XMM25,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM21,%XMM26,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM20,%XMM26,%XMM26	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM18,%XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD132SD %XMM15,%XMM26,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VADDSD %XMM27,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM3,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD %XMM9,%XMM9,%XMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD213SD (%R11,%RAX,8),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM3,(%R11,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM30,%XMM30,%XMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD213SD (%R14,%RAX,8),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM3,(%R14,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM29,%XMM29,%XMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD213SD (%R15,%RAX,8),%XMM1,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM3,(%R15,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM31,%XMM31,%XMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD213SD (%RDX,%RAX,8),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM3,(%RDX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM5,%XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD213SD (%RSI,%RAX,8),%XMM1,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM3,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM5,%XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD213SD (%RBX,%RAX,8),%XMM4,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM2,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM29,%XMM29,%XMM2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD213SD (%R12,%RAX,8),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM2,(%R12,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMADD213SD (%R8,%RAX,8),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM3,(%R8,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMADD213SD (%RCX,%RAX,8),%XMM4,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM1,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0xf0(%RSP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VFMADD213SD (%RCX,%RAX,8),%XMM4,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RCX,0xe8(%RSP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JNE 4820f0 <_ZN16miniqmcreference19MultiBsplineEvalRef12evaluate_vghIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_S9_S9_m+0x7e0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.54	9.97	0.28	14.91	0.16	17.13	0.07	17.2	0.04	12.44	0.02	8.34	0.01	7.22

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	10.59	19.83
2x2	4	0.54	0.9	1.6666666666667	11.4	21.53
2x4	8	0.28	0.92	3.3333333333333	11.7	20.6
2x8	16	0.16	0.91	5.6666666666667	12.97	20.39
2x16	32	0.07	0.77	11.333333333333	18.71	18.45
2x32	64	0.04	0.93	22	12.83	12.99
2x64	128	0.02	0.76	43.333333333333	15.84	8.49
2x96	192	0.01	0.61	64.666666666667	17.35	7.29

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency