OV - - Loop 830

	Loop Id: 830	Module: exec	Source: MultiBsplineRef.hpp:68-71	Coverage: 9.6%

0x4779d0 VMULPD	(%R14,%RAX,1),%ZMM6,%ZMM26    [3]

0x4779d7 VMULPD	(%R9,%RAX,1),%ZMM4,%ZMM15    [2]

0x4779de VMULPD	(%R11,%RAX,1),%ZMM6,%ZMM0    [9]

0x4779e5 VMULPD	(%R8,%RAX,1),%ZMM4,%ZMM28    [12]

0x4779ec VFMADD231PD	(%RBX,%RAX,1),%ZMM5,%ZMM15    [7]

0x4779f3 VFMADD231PD	(%RDI,%RAX,1),%ZMM7,%ZMM26    [8]

0x4779fa VADDPD	%ZMM15,%ZMM26,%ZMM27

0x477a00 VFMADD213PD	(%R12,%RAX,1),%ZMM11,%ZMM27    [4]

0x477a07 VMULPD	0x40(%RAX,%R11,1),%ZMM6,%ZMM14    [10]

0x477a0f VMULPD	0x40(%R8,%RAX,1),%ZMM4,%ZMM30    [12]

0x477a17 VFMADD231PD	(%RSI,%RAX,1),%ZMM7,%ZMM0    [6]

0x477a1e VFMADD231PD	(%R10,%RAX,1),%ZMM5,%ZMM28    [5]

0x477a25 VADDPD	%ZMM28,%ZMM0,%ZMM9

0x477a2b VFMADD231PD	0x40(%RAX,%RSI,1),%ZMM7,%ZMM14    [1]

0x477a33 VFMADD231PD	0x40(%R10,%RAX,1),%ZMM5,%ZMM30    [5]

0x477a3b VADDPD	%ZMM30,%ZMM14,%ZMM15

0x477a41 VMULPD	0x40(%R14,%RAX,1),%ZMM6,%ZMM1    [3]

0x477a49 VMULPD	0x40(%R9,%RAX,1),%ZMM4,%ZMM29    [2]

0x477a51 VFMADD231PD	0x40(%RDI,%RAX,1),%ZMM7,%ZMM1    [8]

0x477a59 VFMADD231PD	0x40(%RBX,%RAX,1),%ZMM5,%ZMM29    [7]

0x477a61 VFMADD132PD	%ZMM10,%ZMM27,%ZMM9

0x477a67 VADDPD	%ZMM29,%ZMM1,%ZMM8

0x477a6d VFMADD213PD	0x40(%R12,%RAX,1),%ZMM11,%ZMM8    [4]

0x477a75 VFMADD132PD	%ZMM10,%ZMM8,%ZMM15

0x477a7b VMOVUPD	%ZMM9,(%R12,%RAX,1)    [4]

0x477a82 VMOVUPD	%ZMM15,0x40(%R12,%RAX,1)    [4]

0x477a8a SUB	$-0x80,%RAX

0x477a8e CMP	%RAX,0xf0(%RSP)    [11]

0x477a96 JNE	4779d0

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 68 - 71

--------------------------------------------------------------------------------

68:       for (size_t n = 0; n < num_splines; n++)

69:         vals[n] += pre00 *

70:             (c[0] * coefs[n] + c[1] * coefs[n + zs] + c[2] * coefs[n + 2 * zs] +

71:              c[3] * coefs[n + 3 * zs]);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks	P8, P9,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE
Source	MultiBsplineRef.hpp:68-71
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.00
CQA cycles if no scalar integer	20.00
CQA cycles if FP arith vectorized	20.00
CQA cycles if fully vectorized	20.00
Front-end cycles	5.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	13.00
P5 cycles	13.00
P6 cycles	13.00
P7 cycles	20.00
P8 cycles	20.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	30.00
Nb loads	19.00
Nb stores	2.00
Nb stack references	1.00
FLOP/cycle	14.40
Nb FLOP add-sub	32.00
Nb FLOP mul	64.00
Nb FLOP fma	96.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.40
Bytes prefetched	0.00
Bytes loaded	1160.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	7.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks	P8, P9,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE
Source	MultiBsplineRef.hpp:68-71
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.00
CQA cycles if no scalar integer	20.00
CQA cycles if FP arith vectorized	20.00
CQA cycles if fully vectorized	20.00
Front-end cycles	5.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	13.00
P5 cycles	13.00
P6 cycles	13.00
P7 cycles	20.00
P8 cycles	20.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	30.00
Nb loads	19.00
Nb stores	2.00
Nb stack references	1.00
FLOP/cycle	14.40
Nb FLOP add-sub	32.00
Nb FLOP mul	64.00
Nb FLOP fma	96.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.40
Bytes prefetched	0.00
Bytes loaded	1160.00
Bytes stored	128.00
Stride 0	1.00
Stride 1	7.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE
Source file and lines	MultiBsplineRef.hpp:68-71
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:68-71.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 20.00 to 13.00 cycles (1.54x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 96 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 2 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

24 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 288 FP arithmetical operations:

128: addition or subtraction (96 inside FMA instructions)
160: multiply (96 inside FMA instructions)

The binary loop is loading 1160 bytes (145 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	29
nb uops	30
loop length	204
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	17
nb stack references	1
ADD-SUB / MUL ratio	0.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	7.00	7.00	7.00	10.00	10.00	2.00	2.00	2.00	2.00
cycles	0.50	0.50	0.25	0.25	0.50	13.00	13.00	13.00	20.00	20.00	4.00	4.00	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.00
Dispatch	20.00
Data deps.	1.00
Overall L1	20.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

60% of peak load performance is reached (58.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (6.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4779d0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMULPD (%R14,%RAX,1),%ZMM6,%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD (%R9,%RAX,1),%ZMM4,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD (%R11,%RAX,1),%ZMM6,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD (%R8,%RAX,1),%ZMM4,%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD (%RBX,%RAX,1),%ZMM5,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD (%RDI,%RAX,1),%ZMM7,%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM15,%ZMM26,%ZMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD213PD (%R12,%RAX,1),%ZMM11,%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMULPD 0x40(%RAX,%R11,1),%ZMM6,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0x40(%R8,%RAX,1),%ZMM4,%ZMM30	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD (%RSI,%RAX,1),%ZMM7,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD (%R10,%RAX,1),%ZMM5,%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM28,%ZMM0,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD231PD 0x40(%RAX,%RSI,1),%ZMM7,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x40(%R10,%RAX,1),%ZMM5,%ZMM30	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM30,%ZMM14,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD 0x40(%R14,%RAX,1),%ZMM6,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0x40(%R9,%RAX,1),%ZMM4,%ZMM29	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD 0x40(%RDI,%RAX,1),%ZMM7,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x40(%RBX,%RAX,1),%ZMM5,%ZMM29	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD132PD %ZMM10,%ZMM27,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM29,%ZMM1,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD213PD 0x40(%R12,%RAX,1),%ZMM11,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD132PD %ZMM10,%ZMM8,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVUPD %ZMM9,(%R12,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM15,0x40(%R12,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
SUB $-0x80,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RAX,0xf0(%RSP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JNE 4779d0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x610>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE
Source file and lines	MultiBsplineRef.hpp:68-71
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 96 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 2 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

24 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 288 FP arithmetical operations:

128: addition or subtraction (96 inside FMA instructions)
160: multiply (96 inside FMA instructions)

The binary loop is loading 1160 bytes (145 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	29
nb uops	30
loop length	204
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	17
nb stack references	1
ADD-SUB / MUL ratio	0.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	7.00	7.00	7.00	10.00	10.00	2.00	2.00	2.00	2.00
cycles	0.50	0.50	0.25	0.25	0.50	13.00	13.00	13.00	20.00	20.00	4.00	4.00	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.00
Dispatch	20.00
Data deps.	1.00
Overall L1	20.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

60% of peak load performance is reached (58.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (6.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4779d0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMULPD (%R14,%RAX,1),%ZMM6,%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD (%R9,%RAX,1),%ZMM4,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD (%R11,%RAX,1),%ZMM6,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD (%R8,%RAX,1),%ZMM4,%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD (%RBX,%RAX,1),%ZMM5,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD (%RDI,%RAX,1),%ZMM7,%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM15,%ZMM26,%ZMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD213PD (%R12,%RAX,1),%ZMM11,%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMULPD 0x40(%RAX,%R11,1),%ZMM6,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0x40(%R8,%RAX,1),%ZMM4,%ZMM30	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD (%RSI,%RAX,1),%ZMM7,%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD (%R10,%RAX,1),%ZMM5,%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM28,%ZMM0,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD231PD 0x40(%RAX,%RSI,1),%ZMM7,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x40(%R10,%RAX,1),%ZMM5,%ZMM30	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM30,%ZMM14,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD 0x40(%R14,%RAX,1),%ZMM6,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0x40(%R9,%RAX,1),%ZMM4,%ZMM29	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD 0x40(%RDI,%RAX,1),%ZMM7,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x40(%RBX,%RAX,1),%ZMM5,%ZMM29	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD132PD %ZMM10,%ZMM27,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM29,%ZMM1,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD213PD 0x40(%R12,%RAX,1),%ZMM11,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD132PD %ZMM10,%ZMM8,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVUPD %ZMM9,(%R12,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM15,0x40(%R12,%RAX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
SUB $-0x80,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RAX,0xf0(%RSP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JNE 4779d0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x610>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.53	5.06	0.24	8.78	0.13	10.98	0.04	16.03	0.01	22.29	0	25.55	0	27.89

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	4.4	9.6
2x2	4	0.53	0.88	1.6666666666667	5.32	10.66
2x4	8	0.24	0.8	3.3333333333333	5.99	11.54
2x8	16	0.13	0.71	5.6666666666667	6.16	12.56
2x16	32	0.04	0.41	11.333333333333	13.59	16.64
2x32	64	0.01	0.26	22	19.56	22.56
2x64	128	0	0.12	43.333333333333	40.97	25.62
2x96	192	0	0.08	64.666666666667	63.95	27.92

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency