OV - - Loop 597

	Loop Id: 597	Module: exec	Source: TwoBodyJastrowRef.h:397-398	Coverage: 0.04%

0x455e69 VMOVUPD	(%R14,%RDI,1),%ZMM11    [2]

0x455e70 VMOVUPD	(%RAX,%RDI,1),%ZMM8    [3]

0x455e77 VMOVUPD	0x40(%RAX,%RDI,1),%ZMM7    [3]

0x455e7f VFNMADD132PD	(%RDX,%RDI,1),%ZMM8,%ZMM11    [5]

0x455e86 VMOVUPD	0x80(%RAX,%RDI,1),%ZMM0    [3]

0x455e8e VMOVUPD	%ZMM11,(%RAX,%RDI,1)    [3]

0x455e95 VMOVUPD	0xc0(%RAX,%RDI,1),%ZMM13    [3]

0x455e9d VMOVUPD	0x40(%R14,%RDI,1),%ZMM5    [2]

0x455ea5 VMOVUPD	0x100(%RAX,%RDI,1),%ZMM2    [3]

0x455ead VFNMADD132PD	0x40(%RDI,%RDX,1),%ZMM7,%ZMM5    [1]

0x455eb5 VMOVUPD	0x140(%RAX,%RDI,1),%ZMM3    [3]

0x455ebd VMOVUPD	%ZMM5,0x40(%RAX,%RDI,1)    [3]

0x455ec5 VMOVUPD	0x180(%RAX,%RDI,1),%ZMM6    [3]

0x455ecd VMOVUPD	0x80(%R14,%RDI,1),%ZMM4    [2]

0x455ed5 VMOVUPD	0x1c0(%RAX,%RDI,1),%ZMM8    [3]

0x455edd VFNMADD132PD	0x80(%RDI,%RDX,1),%ZMM0,%ZMM4    [1]

0x455ee5 VMOVUPD	%ZMM4,0x80(%RAX,%RDI,1)    [3]

0x455eed VMOVUPD	0xc0(%R14,%RDI,1),%ZMM14    [2]

0x455ef5 VFNMADD132PD	0xc0(%RDI,%RDX,1),%ZMM13,%ZMM14    [1]

0x455efd VMOVUPD	%ZMM14,0xc0(%RAX,%RDI,1)    [3]

0x455f05 VMOVUPD	0x100(%R14,%RDI,1),%ZMM15    [2]

0x455f0d VFNMADD132PD	0x100(%RDI,%RDX,1),%ZMM2,%ZMM15    [1]

0x455f15 VMOVUPD	%ZMM15,0x100(%RAX,%RDI,1)    [3]

0x455f1d VMOVUPD	0x140(%R14,%RDI,1),%ZMM1    [2]

0x455f25 VFNMADD132PD	0x140(%RDI,%RDX,1),%ZMM3,%ZMM1    [1]

0x455f2d VMOVUPD	%ZMM1,0x140(%RAX,%RDI,1)    [3]

0x455f35 VMOVUPD	0x180(%R14,%RDI,1),%ZMM12    [2]

0x455f3d VFNMADD132PD	0x180(%RDI,%RDX,1),%ZMM6,%ZMM12    [1]

0x455f45 VMOVUPD	%ZMM12,0x180(%RAX,%RDI,1)    [3]

0x455f4d VMOVUPD	0x1c0(%R14,%RDI,1),%ZMM11    [2]

0x455f55 VFNMADD132PD	0x1c0(%RDI,%RDX,1),%ZMM8,%ZMM11    [1]

0x455f5d VMOVUPD	%ZMM11,0x1c0(%RAX,%RDI,1)    [3]

0x455f65 ADD	$0x200,%RDI

0x455f6c CMP	%RDI,0x158(%RSP)    [4]

0x455f74 JNE	455e69

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 397 - 398

--------------------------------------------------------------------------------

397:         for (int jat = 0; jat < iat; jat++)

398:           save_g[jat] -= du[jat] * dX[jat];

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.38
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE
Source	TwoBodyJastrowRef.h:397-398
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	19.00
CQA cycles if no scalar integer	19.00
CQA cycles if FP arith vectorized	19.00
CQA cycles if fully vectorized	19.00
Front-end cycles	7.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	19.00
P5 cycles	19.00
P6 cycles	19.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	42.00
Nb loads	25.00
Nb stores	8.00
Nb stack references	1.00
FLOP/cycle	6.74
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	108.21
Bytes prefetched	0.00
Bytes loaded	1544.00
Bytes stored	512.00
Stride 0	1.00
Stride 1	2.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.38
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE
Source	TwoBodyJastrowRef.h:397-398
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	19.00
CQA cycles if no scalar integer	19.00
CQA cycles if FP arith vectorized	19.00
CQA cycles if fully vectorized	19.00
Front-end cycles	7.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	19.00
P5 cycles	19.00
P6 cycles	19.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	42.00
Nb loads	25.00
Nb stores	8.00
Nb stack references	1.00
FLOP/cycle	6.74
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	108.21
Bytes prefetched	0.00
Bytes loaded	1544.00
Bytes stored	512.00
Stride 0	1.00
Stride 1	2.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE
Source file and lines	TwoBodyJastrowRef.h:397-398
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:397-398.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 19.00 to 8.00 cycles (2.37x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 64 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 8 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

64: addition or subtraction (all inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary loop is loading 1544 bytes (193 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	35
nb uops	42
loop length	273
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	14
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	11.00	11.00	11.00	4.00	4.00	0.00	0.00	8.00	8.00
cycles	0.50	0.50	0.25	0.25	0.50	19.00	19.00	19.00	8.00	8.00	0.00	0.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.00
Dispatch	19.00
Data deps.	1.00
Overall L1	19.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.00 cycles. At this rate:

84% of peak load performance is reached (81.26 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (26.95 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 455e69

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R14,%RDI,1),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD (%RAX,%RDI,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x40(%RAX,%RDI,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD132PD (%RDX,%RDI,1),%ZMM8,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD 0x80(%RAX,%RDI,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM11,(%RAX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0xc0(%RAX,%RDI,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x40(%R14,%RDI,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x100(%RAX,%RDI,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD132PD 0x40(%RDI,%RDX,1),%ZMM7,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD 0x140(%RAX,%RDI,1),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM5,0x40(%RAX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x180(%RAX,%RDI,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x80(%R14,%RDI,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x1c0(%RAX,%RDI,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD132PD 0x80(%RDI,%RDX,1),%ZMM0,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD %ZMM4,0x80(%RAX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0xc0(%R14,%RDI,1),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD132PD 0xc0(%RDI,%RDX,1),%ZMM13,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD %ZMM14,0xc0(%RAX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x100(%R14,%RDI,1),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD132PD 0x100(%RDI,%RDX,1),%ZMM2,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD %ZMM15,0x100(%RAX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x140(%R14,%RDI,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD132PD 0x140(%RDI,%RDX,1),%ZMM3,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD %ZMM1,0x140(%RAX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x180(%R14,%RDI,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD132PD 0x180(%RDI,%RDX,1),%ZMM6,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD %ZMM12,0x180(%RAX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x1c0(%R14,%RDI,1),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD132PD 0x1c0(%RDI,%RDX,1),%ZMM8,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD %ZMM11,0x1c0(%RAX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x200,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %RDI,0x158(%RSP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
JNE 455e69 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE+0x16a9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE
Source file and lines	TwoBodyJastrowRef.h:397-398
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 19.00 to 8.00 cycles (2.37x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 64 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 8 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

64: addition or subtraction (all inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary loop is loading 1544 bytes (193 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	35
nb uops	42
loop length	273
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	14
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	11.00	11.00	11.00	4.00	4.00	0.00	0.00	8.00	8.00
cycles	0.50	0.50	0.25	0.25	0.50	19.00	19.00	19.00	8.00	8.00	0.00	0.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.00
Dispatch	19.00
Data deps.	1.00
Overall L1	19.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.00 cycles. At this rate:

84% of peak load performance is reached (81.26 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (26.95 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 455e69

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R14,%RDI,1),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD (%RAX,%RDI,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x40(%RAX,%RDI,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD132PD (%RDX,%RDI,1),%ZMM8,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD 0x80(%RAX,%RDI,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM11,(%RAX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0xc0(%RAX,%RDI,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x40(%R14,%RDI,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x100(%RAX,%RDI,1),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD132PD 0x40(%RDI,%RDX,1),%ZMM7,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD 0x140(%RAX,%RDI,1),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD %ZMM5,0x40(%RAX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x180(%RAX,%RDI,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x80(%R14,%RDI,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x1c0(%RAX,%RDI,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD132PD 0x80(%RDI,%RDX,1),%ZMM0,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD %ZMM4,0x80(%RAX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0xc0(%R14,%RDI,1),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD132PD 0xc0(%RDI,%RDX,1),%ZMM13,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD %ZMM14,0xc0(%RAX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x100(%R14,%RDI,1),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD132PD 0x100(%RDI,%RDX,1),%ZMM2,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD %ZMM15,0x100(%RAX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x140(%R14,%RDI,1),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD132PD 0x140(%RDI,%RDX,1),%ZMM3,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD %ZMM1,0x140(%RAX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x180(%R14,%RDI,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD132PD 0x180(%RDI,%RDX,1),%ZMM6,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD %ZMM12,0x180(%RAX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD 0x1c0(%R14,%RDI,1),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VFNMADD132PD 0x1c0(%RDI,%RDX,1),%ZMM8,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	1
VMOVUPD %ZMM11,0x1c0(%RAX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0x200,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %RDI,0x158(%RSP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
JNE 455e69 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE+0x16a9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.6	0.02	0.6	0.01	0.35	0.02	0.18	0.02	0.09	0.02	0.05	0.01	0.02	0.01

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.02	0.04
2x2	4	0.6	1	1.6666666666667	0.02	0.04
2x4	8	0.6	2	3.3333333333333	0.02	0.02
2x8	16	0.35	2	5.6666666666667	0.02	0.03
2x16	32	0.18	2	11.333333333333	0.02	0.02
2x32	64	0.09	2	22	0.03	0.02
2x64	128	0.05	2	43.333333333333	0.03	0.01
2x96	192	0.02	1	64.666666666667	0.03	0.01

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency