OV - - Loop 353

	Loop Id: 353	Module: exec	Source: BsplineFunctor.h:246-260	Coverage: 0.07%

0x4300a0 VMULPD	(%RDX),%ZMM29,%ZMM12    [66]

0x4300a6 VMULPD	0x40(%RDX),%ZMM29,%ZMM8    [66]

0x4300ad SUB	$-0x80,%RDX

0x4300b1 VRNDSCALEPD	$0xb,%ZMM12,%ZMM6

0x4300b8 VCVTTPD2DQ	%ZMM12,%YMM13

0x4300be VCVTTPD2DQ	%ZMM8,%YMM15

0x4300c4 VPMOVSXDQ	%YMM13,%ZMM10

0x4300ca VPMOVSXDQ	%YMM15,%ZMM14

0x4300d0 VINSERTI64X4	$0x1,%YMM15,%ZMM13,%ZMM1

0x4300d7 VSUBPD	%ZMM6,%ZMM12,%ZMM0

0x4300dd VEXTRACTI64X4	$0x1,%ZMM10,%YMM12

0x4300e4 VPEXTRQ	$0x1,%XMM10,%RSI

0x4300ea VEXTRACTI64X2	$0x1,%YMM10,%XMM5

0x4300f1 VPEXTRQ	$0x1,%XMM12,%R12

0x4300f7 VMOVQ	%XMM10,%R8

0x4300fc VMOVQ	%XMM12,%R13

0x430101 VMOVSD	(%RAX,%R13,8),%XMM9    [19]

0x430107 VMOVSD	(%RAX,%R8,8),%XMM13    [23]

0x43010d VMOVHPD	(%RAX,%R12,8),%XMM9,%XMM4    [43]

0x430113 VMULPD	%ZMM0,%ZMM0,%ZMM7

0x430119 VMOVQ	%XMM14,%R8

0x43011e VALIGNQ	$0x3,%YMM10,%YMM10,%YMM3

0x430125 VMOVQ	%XMM5,%R11

0x43012a VMULPD	%ZMM0,%ZMM7,%ZMM17

0x430130 VEXTRACTI64X2	$0x1,%YMM12,%XMM15

0x430137 VMOVQ	%XMM3,%R9

0x43013c VMOVSD	(%RAX,%R11,8),%XMM3    [49]

0x430142 VALIGNQ	$0x3,%YMM12,%YMM12,%YMM6

0x430149 VMOVQ	%XMM15,%R14

0x43014e VMOVHPD	(%RAX,%R9,8),%XMM3,%XMM12    [4]

0x430154 VMOVHPD	(%RAX,%RSI,8),%XMM13,%XMM15    [50]

0x430159 VPEXTRQ	$0x1,%XMM14,%RSI

0x43015f VRNDSCALEPD	$0xb,%ZMM8,%ZMM11

0x430166 VMOVQ	%XMM6,%RCX

0x43016b VINSERTF128	$0x1,%XMM12,%YMM15,%YMM6

0x430171 VSUBPD	%ZMM11,%ZMM8,%ZMM2

0x430177 VMOVSD	(%RAX,%R14,8),%XMM11    [30]

0x43017d VMOVHPD	(%RAX,%RCX,8),%XMM11,%XMM10    [7]

0x430182 VINSERTF128	$0x1,%XMM10,%YMM4,%YMM5

0x430188 VEXTRACTI64X2	$0x1,%YMM14,%XMM9

0x43018f VINSERTF64X4	$0x1,%YMM5,%ZMM6,%ZMM4

0x430196 VMULPD	%ZMM2,%ZMM2,%ZMM8

0x43019c VMOVAPD	%ZMM2,%ZMM18

0x4301a2 VFMADD132PD	%ZMM22,%ZMM21,%ZMM18

0x4301a8 VMULPD	%ZMM2,%ZMM8,%ZMM16

0x4301ae VALIGNQ	$0x3,%YMM14,%YMM14,%YMM5

0x4301b5 VEXTRACTI64X4	$0x1,%ZMM14,%YMM14

0x4301bc VMOVQ	%XMM9,%R9

0x4301c1 VMOVQ	%XMM14,%R12

0x4301c6 VPEXTRQ	$0x1,%XMM14,%R11

0x4301cc VMOVSD	(%RAX,%R12,8),%XMM11    [17]

0x4301d2 VMOVHPD	(%RAX,%R11,8),%XMM11,%XMM10    [25]

0x4301d8 VMULPD	%ZMM28,%ZMM8,%ZMM11

0x4301de VEXTRACTI64X2	$0x1,%YMM14,%XMM12

0x4301e5 VMOVQ	%XMM5,%RCX

0x4301ea VMOVSD	(%RAX,%R8,8),%XMM5    [31]

0x4301f0 VFMADD231PD	%ZMM27,%ZMM16,%ZMM11

0x4301f6 VALIGNQ	$0x3,%YMM14,%YMM14,%YMM13

0x4301fd VMOVSD	(%RAX,%R9,8),%XMM14    [38]

0x430203 VMOVQ	%XMM12,%R13

0x430208 VMOVHPD	(%RAX,%RCX,8),%XMM14,%XMM3    [47]

0x43020d VMOVHPD	(%RAX,%RSI,8),%XMM5,%XMM12    [48]

0x430212 VMOVSD	(%RAX,%R13,8),%XMM15    [18]

0x430218 VMOVQ	%XMM13,%R14

0x43021d VINSERTF128	$0x1,%XMM3,%YMM12,%YMM13

0x430223 VMOVHPD	(%RAX,%R14,8),%XMM15,%XMM6    [22]

0x430229 VMULPD	%ZMM28,%ZMM7,%ZMM15

0x43022f VINSERTF128	$0x1,%XMM6,%YMM10,%YMM9

0x430235 VMOVAPD	%ZMM2,%ZMM10

0x43023b VMOVAPD	%ZMM0,%ZMM6

0x430241 VFMADD132PD	%ZMM26,%ZMM25,%ZMM10

0x430247 VFMADD132PD	%ZMM26,%ZMM25,%ZMM6

0x43024d VINSERTF64X4	$0x1,%YMM9,%ZMM13,%ZMM5

0x430254 VPADDD	-0x2b0(%RBP),%ZMM1,%ZMM9    [56]

0x43025e VFMADD231PD	%ZMM27,%ZMM17,%ZMM15

0x430264 VADDPD	%ZMM10,%ZMM11,%ZMM12

0x43026a VADDPD	%ZMM6,%ZMM15,%ZMM13

0x430270 VPMOVSXDQ	%YMM9,%ZMM14

0x430276 VEXTRACTI32X8	$0x1,%ZMM9,%YMM3

0x43027d VPMOVSXDQ	%YMM3,%ZMM11

0x430283 VEXTRACTI64X2	$0x1,%YMM14,%XMM10

0x43028a VPEXTRQ	$0x1,%XMM14,%RSI

0x430290 VMOVQ	%XMM14,%R8

0x430295 VALIGNQ	$0x3,%YMM14,%YMM14,%YMM9

0x43029c VEXTRACTI64X4	$0x1,%ZMM14,%YMM14

0x4302a3 VMOVQ	%XMM10,%R11

0x4302a8 VMOVQ	%XMM14,%R13

0x4302ad VPEXTRQ	$0x1,%XMM14,%R12

0x4302b3 VEXTRACTI64X2	$0x1,%YMM14,%XMM6

0x4302ba VMOVQ	%XMM9,%R9

0x4302bf VALIGNQ	$0x3,%YMM14,%YMM14,%YMM15

0x4302c6 VMOVSD	(%RAX,%R13,8),%XMM14    [16]

0x4302cc VMOVQ	%XMM6,%R14

0x4302d1 VMOVHPD	(%RAX,%R12,8),%XMM14,%XMM3    [42]

0x4302d7 VMOVSD	(%RAX,%R14,8),%XMM10    [54]

0x4302dd VMOVQ	%XMM15,%RCX

0x4302e2 VMOVSD	(%RAX,%R11,8),%XMM15    [35]

0x4302e8 VMOVHPD	(%RAX,%RCX,8),%XMM10,%XMM9    [41]

0x4302ed VMOVSD	(%RAX,%R8,8),%XMM10    [1]

0x4302f3 VMOVHPD	(%RAX,%RSI,8),%XMM10,%XMM14    [62]

0x4302f8 VMOVQ	%XMM11,%R8

0x4302fd VINSERTF128	$0x1,%XMM9,%YMM3,%YMM6

0x430303 VMOVHPD	(%RAX,%R9,8),%XMM15,%XMM9    [37]

0x430309 VPEXTRQ	$0x1,%XMM11,%RSI

0x43030f VINSERTF128	$0x1,%XMM9,%YMM14,%YMM3

0x430315 VEXTRACTI64X2	$0x1,%YMM11,%XMM9

0x43031c VINSERTF64X4	$0x1,%YMM6,%ZMM3,%ZMM10

0x430323 VALIGNQ	$0x3,%YMM11,%YMM11,%YMM14

0x43032a VEXTRACTI64X4	$0x1,%ZMM11,%YMM11

0x430331 VMOVQ	%XMM9,%R11

0x430336 VMOVQ	%XMM11,%R13

0x43033b VPEXTRQ	$0x1,%XMM11,%R12

0x430341 VEXTRACTI64X2	$0x1,%YMM11,%XMM6

0x430348 VMOVQ	%XMM14,%R9

0x43034d VALIGNQ	$0x3,%YMM11,%YMM11,%YMM15

0x430354 VMOVSD	(%RAX,%R13,8),%XMM11    [11]

0x43035a VMOVQ	%XMM6,%R14

0x43035f VMOVHPD	(%RAX,%R12,8),%XMM11,%XMM3    [29]

0x430365 VMOVSD	(%RAX,%R11,8),%XMM6    [15]

0x43036b VMOVSD	(%RAX,%R14,8),%XMM9    [53]

0x430371 VMOVQ	%XMM15,%RCX

0x430376 VMOVHPD	(%RAX,%RCX,8),%XMM9,%XMM14    [40]

0x43037b VINSERTF128	$0x1,%XMM14,%YMM3,%YMM15

0x430381 VMOVHPD	(%RAX,%R9,8),%XMM6,%XMM14    [65]

0x430387 VMOVSD	(%RAX,%R8,8),%XMM9    [3]

0x43038d VMOVHPD	(%RAX,%RSI,8),%XMM9,%XMM11    [61]

0x430392 VINSERTF128	$0x1,%XMM14,%YMM11,%YMM3

0x430398 VPADDD	-0x2f0(%RBP),%ZMM1,%ZMM11    [56]

0x4303a2 VMOVAPD	%ZMM0,%ZMM6

0x4303a8 VMOVAPD	-0x170(%RBP),%ZMM20    [56]

0x4303b2 VINSERTF64X4	$0x1,%YMM15,%ZMM3,%ZMM9

0x4303b9 VMOVAPD	-0x1f0(%RBP),%ZMM19    [56]

0x4303c3 VPADDD	-0x330(%RBP),%ZMM1,%ZMM1    [56]

0x4303cd VMULPD	%ZMM23,%ZMM7,%ZMM15

0x4303d3 VFMADD132PD	%ZMM22,%ZMM21,%ZMM6

0x4303d9 VMULPD	%ZMM23,%ZMM8,%ZMM14

0x4303df VFMADD231PD	%ZMM24,%ZMM17,%ZMM15

0x4303e5 VEXTRACTI32X8	$0x1,%ZMM11,%YMM3

0x4303ec VFMADD231PD	%ZMM24,%ZMM16,%ZMM14

0x4303f2 VPMOVSXDQ	%YMM3,%ZMM3

0x4303f8 VADDPD	%ZMM6,%ZMM15,%ZMM15

0x4303fe VPMOVSXDQ	%YMM11,%ZMM6

0x430404 VADDPD	%ZMM14,%ZMM18,%ZMM18

0x43040a VEXTRACTI64X2	$0x1,%YMM6,%XMM14

0x430411 VPEXTRQ	$0x1,%XMM6,%RSI

0x430417 VMOVQ	%XMM6,%R8

0x43041c VALIGNQ	$0x3,%YMM6,%YMM6,%YMM11

0x430423 VEXTRACTI64X4	$0x1,%ZMM6,%YMM6

0x43042a VMOVQ	%XMM14,%R9

0x43042f VMOVQ	%XMM6,%R12

0x430434 VPEXTRQ	$0x1,%XMM6,%R11

0x43043a VEXTRACTI64X2	$0x1,%YMM6,%XMM14

0x430441 VMOVQ	%XMM11,%RCX

0x430446 VMOVSD	(%RAX,%R8,8),%XMM11    [52]

0x43044c VMOVHPD	(%RAX,%RSI,8),%XMM11,%XMM11    [60]

0x430451 VMOVQ	%XMM3,%R8

0x430456 VPEXTRQ	$0x1,%XMM3,%RSI

0x43045c VALIGNQ	$0x3,%YMM6,%YMM6,%YMM6

0x430463 VMOVQ	%XMM14,%R13

0x430468 VMOVSD	(%RAX,%R13,8),%XMM14    [63]

0x43046e VMOVQ	%XMM6,%R14

0x430473 VMOVSD	(%RAX,%R12,8),%XMM6    [51]

0x430479 VMOVHPD	(%RAX,%R11,8),%XMM6,%XMM6    [24]

0x43047f VMOVHPD	(%RAX,%R14,8),%XMM14,%XMM14    [34]

0x430485 VINSERTF128	$0x1,%XMM14,%YMM6,%YMM6

0x43048b VMOVSD	(%RAX,%R9,8),%XMM14    [64]

0x430491 VMOVHPD	(%RAX,%RCX,8),%XMM14,%XMM14    [10]

0x430496 VINSERTF128	$0x1,%XMM14,%YMM11,%YMM14

0x43049c VINSERTF64X4	$0x1,%YMM6,%ZMM14,%ZMM11

0x4304a3 VALIGNQ	$0x3,%YMM3,%YMM3,%YMM6

0x4304aa VEXTRACTI64X2	$0x1,%YMM3,%XMM14

0x4304b1 VEXTRACTI64X4	$0x1,%ZMM3,%YMM3

0x4304b8 VMOVQ	%XMM6,%R9

0x4304bd VMOVQ	%XMM3,%R13

0x4304c2 VPEXTRQ	$0x1,%XMM3,%R12

0x4304c8 VEXTRACTI64X2	$0x1,%YMM3,%XMM6

0x4304cf VMOVQ	%XMM14,%R11

0x4304d4 VALIGNQ	$0x3,%YMM3,%YMM3,%YMM3

0x4304db VMOVQ	%XMM6,%R14

0x4304e0 VMOVSD	(%RAX,%R13,8),%XMM6    [45]

0x4304e6 VMOVSD	(%RAX,%R14,8),%XMM14    [32]

0x4304ec VMOVQ	%XMM3,%RCX

0x4304f1 VMOVHPD	(%RAX,%RCX,8),%XMM14,%XMM3    [44]

0x4304f6 VMOVHPD	(%RAX,%R12,8),%XMM6,%XMM14    [28]

0x4304fc VINSERTF128	$0x1,%XMM3,%YMM14,%YMM6

0x430502 VMOVSD	(%RAX,%R11,8),%XMM3    [36]

0x430508 VMOVHPD	(%RAX,%R9,8),%XMM3,%XMM14    [33]

0x43050e VMOVSD	(%RAX,%R8,8),%XMM3    [46]

0x430514 VMOVHPD	(%RAX,%RSI,8),%XMM3,%XMM3    [59]

0x430519 VINSERTF128	$0x1,%XMM14,%YMM3,%YMM14

0x43051f VINSERTF64X4	$0x1,%YMM6,%ZMM14,%ZMM3

0x430526 VMOVAPD	-0x1b0(%RBP),%ZMM14    [56]

0x430530 VMULPD	%ZMM14,%ZMM7,%ZMM6

0x430536 VMULPD	%ZMM14,%ZMM8,%ZMM14

0x43053c VFMADD231PD	%ZMM20,%ZMM16,%ZMM14

0x430542 VFMADD231PD	%ZMM20,%ZMM17,%ZMM6

0x430548 VMOVAPD	%ZMM19,%ZMM20

0x43054e VFMADD213PD	-0xf0(%RBP),%ZMM2,%ZMM19    [56]

0x430558 VFMADD213PD	-0xf0(%RBP),%ZMM0,%ZMM20    [56]

0x430562 VMOVAPD	%ZMM20,-0x130(%RBP)    [56]

0x43056c VFMADD132PD	%ZMM31,%ZMM30,%ZMM0

0x430572 VFMADD132PD	%ZMM31,%ZMM30,%ZMM2

0x430578 VADDPD	%ZMM19,%ZMM14,%ZMM14

0x43057e VADDPD	%ZMM20,%ZMM6,%ZMM6

0x430584 VMULPD	%ZMM14,%ZMM3,%ZMM3

0x43058a VMULPD	%ZMM11,%ZMM6,%ZMM6

0x430590 VFMADD231PD	%ZMM18,%ZMM9,%ZMM3

0x430596 VFMADD231PD	%ZMM15,%ZMM10,%ZMM6

0x43059c VPMOVSXDQ	%YMM1,%ZMM9

0x4305a2 VEXTRACTI32X8	$0x1,%ZMM1,%YMM10

0x4305a9 VPMOVSXDQ	%YMM10,%ZMM14

0x4305af VEXTRACTI64X2	$0x1,%YMM9,%XMM11

0x4305b6 VPEXTRQ	$0x1,%XMM9,%RSI

0x4305bc VMOVQ	%XMM9,%R8

0x4305c1 VALIGNQ	$0x3,%YMM9,%YMM9,%YMM10

0x4305c8 VEXTRACTI64X4	$0x1,%ZMM9,%YMM9

0x4305cf VMOVQ	%XMM11,%R11

0x4305d4 VMOVQ	%XMM9,%R13

0x4305d9 VPEXTRQ	$0x1,%XMM9,%R12

0x4305df VMOVSD	(%RAX,%R13,8),%XMM1    [13]

0x4305e5 VEXTRACTI64X2	$0x1,%YMM9,%XMM15

0x4305ec VMOVQ	%XMM10,%R9

0x4305f1 VALIGNQ	$0x3,%YMM9,%YMM9,%YMM11

0x4305f8 VMOVQ	%XMM15,%R14

0x4305fd VMOVHPD	(%RAX,%R12,8),%XMM1,%XMM15    [27]

0x430603 VMOVSD	(%RAX,%R14,8),%XMM10    [39]

0x430609 VMOVQ	%XMM11,%RCX

0x43060e VMOVSD	(%RAX,%R11,8),%XMM11    [9]

0x430614 VMOVHPD	(%RAX,%RCX,8),%XMM10,%XMM9    [8]

0x430619 VMOVHPD	(%RAX,%R9,8),%XMM11,%XMM1    [5]

0x43061f VINSERTF128	$0x1,%XMM9,%YMM15,%YMM10

0x430625 VMOVSD	(%RAX,%R8,8),%XMM9    [14]

0x43062b VMOVHPD	(%RAX,%RSI,8),%XMM9,%XMM15    [58]

0x430630 VMOVQ	%XMM14,%R8

0x430635 VINSERTF128	$0x1,%XMM1,%YMM15,%YMM11

0x43063b VPEXTRQ	$0x1,%XMM14,%RSI

0x430641 VEXTRACTI64X2	$0x1,%YMM14,%XMM15

0x430648 VINSERTF64X4	$0x1,%YMM10,%ZMM11,%ZMM9

0x43064f VALIGNQ	$0x3,%YMM14,%YMM14,%YMM11

0x430656 VEXTRACTI64X4	$0x1,%ZMM14,%YMM14

0x43065d VMOVQ	%XMM15,%R11

0x430662 VMOVQ	%XMM14,%R13

0x430667 VPEXTRQ	$0x1,%XMM14,%R12

0x43066d VMOVSD	(%RAX,%R13,8),%XMM10    [12]

0x430673 VEXTRACTI64X2	$0x1,%YMM14,%XMM1

0x43067a VMOVQ	%XMM11,%R9

0x43067f VALIGNQ	$0x3,%YMM14,%YMM14,%YMM15

0x430686 VMOVQ	%XMM1,%R14

0x43068b VMOVHPD	(%RAX,%R12,8),%XMM10,%XMM1    [26]

0x430691 VMOVSD	(%RAX,%R8,8),%XMM10    [6]

0x430697 VMOVSD	(%RAX,%R14,8),%XMM11    [2]

0x43069d VMOVQ	%XMM15,%RCX

0x4306a2 VMOVHPD	(%RAX,%RCX,8),%XMM11,%XMM14    [20]

0x4306a7 VMOVSD	(%RAX,%R11,8),%XMM11    [21]

0x4306ad VINSERTF128	$0x1,%XMM14,%YMM1,%YMM15

0x4306b3 VMOVHPD	(%RAX,%R9,8),%XMM11,%XMM14    [55]

0x4306b9 VMOVHPD	(%RAX,%RSI,8),%XMM10,%XMM1    [57]

0x4306be VMOVAPD	-0x230(%RBP),%ZMM10    [56]

0x4306c8 VINSERTF128	$0x1,%XMM14,%YMM1,%YMM11

0x4306ce VINSERTF64X4	$0x1,%YMM15,%ZMM11,%ZMM14

0x4306d5 VMOVAPD	-0x270(%RBP),%ZMM15    [56]

0x4306df VMULPD	%ZMM15,%ZMM7,%ZMM7

0x4306e5 VMULPD	%ZMM15,%ZMM8,%ZMM8

0x4306eb VFMADD231PD	%ZMM10,%ZMM17,%ZMM7

0x4306f1 VFMADD231PD	%ZMM10,%ZMM16,%ZMM8

0x4306f7 VADDPD	%ZMM7,%ZMM0,%ZMM0

0x4306fd VADDPD	%ZMM8,%ZMM2,%ZMM2

0x430703 VMULPD	%ZMM9,%ZMM0,%ZMM9

0x430709 VFMADD132PD	%ZMM13,%ZMM9,%ZMM4

0x43070f VMULPD	%ZMM2,%ZMM14,%ZMM13

0x430715 VFMADD132PD	%ZMM12,%ZMM13,%ZMM5

0x43071b VADDPD	%ZMM6,%ZMM4,%ZMM4

0x430721 VADDPD	-0xb0(%RBP),%ZMM4,%ZMM12    [56]

0x43072b VADDPD	%ZMM5,%ZMM3,%ZMM5

0x430731 VADDPD	-0x70(%RBP),%ZMM5,%ZMM6    [56]

0x43073b VMOVAPD	%ZMM12,-0xb0(%RBP)    [56]

0x430745 VMOVAPD	%ZMM6,-0x70(%RBP)    [56]

0x43074f CMP	%RDX,%RDI

0x430752 JNE	4300a0

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 246 - 260

--------------------------------------------------------------------------------

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.58
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.28
Bottlenecks	P8,
Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE
Source	BsplineFunctor.h:246-260
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	77.25
CQA cycles if no scalar integer	77.25
CQA cycles if FP arith vectorized	77.25
CQA cycles if fully vectorized	48.75
Front-end cycles	49.83
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	31.67
P5 cycles	31.67
P6 cycles	31.67
P7 cycles	77.25
P8 cycles	53.17
P9 cycles	46.25
P10 cycles	60.33
P11 cycles	35.00
P12 cycles	35.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	279.00
Nb uops	299.00
Nb loads	78.00
Nb stores	3.00
Nb stack references	12.00
FLOP/cycle	7.46
Nb FLOP add-sub	112.00
Nb FLOP mul	144.00
Nb FLOP fma	160.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.71
Bytes prefetched	0.00
Bytes loaded	1408.00
Bytes stored	192.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	8.00
Vectorization ratio all	53.62
Vectorization ratio load	17.95
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	57.05
Vector-efficiency ratio all	42.75
Vector-efficiency ratio load	28.21
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	31.54

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.58
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.28
Bottlenecks	P8,
Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE
Source	BsplineFunctor.h:246-260
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	77.25
CQA cycles if no scalar integer	77.25
CQA cycles if FP arith vectorized	77.25
CQA cycles if fully vectorized	48.75
Front-end cycles	49.83
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	31.67
P5 cycles	31.67
P6 cycles	31.67
P7 cycles	77.25
P8 cycles	53.17
P9 cycles	46.25
P10 cycles	60.33
P11 cycles	35.00
P12 cycles	35.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	279.00
Nb uops	299.00
Nb loads	78.00
Nb stores	3.00
Nb stack references	12.00
FLOP/cycle	7.46
Nb FLOP add-sub	112.00
Nb FLOP mul	144.00
Nb FLOP fma	160.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.71
Bytes prefetched	0.00
Bytes loaded	1408.00
Bytes stored	192.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	8.00
Vectorization ratio all	53.62
Vectorization ratio load	17.95
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	57.05
Vector-efficiency ratio all	42.75
Vector-efficiency ratio load	28.21
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	31.54

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE
Source file and lines	BsplineFunctor.h:246-260
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:246-260.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 42% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 77.25 to 48.75 cycles (1.58x speedup).

Details

53% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

17% of SSE/AVX loads are used in vector version.
57% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 77.25 to 60.33 cycles (1.28x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 160 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 2 occurrences
VMOVAPD: 3 occurrences
VPEXTRQ: 16 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 16 suboptimal vector unaligned load/store instructions.

Details

VINSERTF128: 16 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

54 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 576 FP arithmetical operations:

272: addition or subtraction (160 inside FMA instructions)
304: multiply (160 inside FMA instructions)

The binary loop is loading 1408 bytes (176 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.36 FP operations per loaded or stored byte.

General properties

nb instructions	279
nb uops	299
loop length	1720
used x86 registers	12
used mmx registers	0
used xmm registers	12
used ymm registers	12
used zmm registers	32
nb stack references	12
ADD-SUB / MUL ratio	0.78

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	49.83 cycles
front end	49.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	27.00	27.00	27.00	46.25	46.17	46.25	46.33	35.00	35.00
cycles	0.50	0.50	0.25	0.25	0.50	31.67	31.67	31.67	77.25	53.17	46.25	60.33	35.00	35.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	49.83
Dispatch	77.25
Data deps.	1.00
Overall L1	77.25

Vectorization ratios

INT

all	46%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	44%

all	59%
load	14%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	53%
load	17%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	57%

Vector efficiency ratios

INT

all	27%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	54%
load	25%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	51%

INT+FP

all	42%
load	28%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 77.25 cycles. At this rate:

18% of peak load performance is reached (18.23 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.49 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4300a0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMULPD (%RDX),%ZMM29,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0x40(%RDX),%ZMM29,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
SUB $-0x80,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VRNDSCALEPD $0xb,%ZMM12,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VCVTTPD2DQ %ZMM12,%YMM13	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	1.33
VCVTTPD2DQ %ZMM8,%YMM15	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	1.33
VPMOVSXDQ %YMM13,%ZMM10	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VPMOVSXDQ %YMM15,%ZMM14	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VINSERTI64X4 $0x1,%YMM15,%ZMM13,%ZMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VSUBPD %ZMM6,%ZMM12,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VEXTRACTI64X4 $0x1,%ZMM10,%YMM12	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VPEXTRQ $0x1,%XMM10,%RSI	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI64X2 $0x1,%YMM10,%XMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VPEXTRQ $0x1,%XMM12,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R13,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RAX,%R8,8),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R12,8),%XMM9,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMULPD %ZMM0,%ZMM0,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVQ %XMM14,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM10,%YMM10,%YMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVQ %XMM5,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMULPD %ZMM0,%ZMM7,%ZMM17	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VEXTRACTI64X2 $0x1,%YMM12,%XMM15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVQ %XMM3,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R11,8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VALIGNQ $0x3,%YMM12,%YMM12,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVQ %XMM15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%R9,8),%XMM3,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%RSI,8),%XMM13,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VPEXTRQ $0x1,%XMM14,%RSI	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VRNDSCALEPD $0xb,%ZMM8,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM6,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VINSERTF128 $0x1,%XMM12,%YMM15,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VSUBPD %ZMM11,%ZMM8,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVSD (%RAX,%R14,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM11,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM10,%YMM4,%YMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VEXTRACTI64X2 $0x1,%YMM14,%XMM9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VINSERTF64X4 $0x1,%YMM5,%ZMM6,%ZMM4	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VMULPD %ZMM2,%ZMM2,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVAPD %ZMM2,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD %ZMM22,%ZMM21,%ZMM18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMULPD %ZMM2,%ZMM8,%ZMM16	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VALIGNQ $0x3,%YMM14,%YMM14,%YMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VEXTRACTI64X4 $0x1,%ZMM14,%YMM14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VMOVQ %XMM9,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM14,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM14,%R11	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RAX,%R12,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R11,8),%XMM11,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMULPD %ZMM28,%ZMM8,%ZMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VEXTRACTI64X2 $0x1,%YMM14,%XMM12	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVQ %XMM5,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R8,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD231PD %ZMM27,%ZMM16,%ZMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VALIGNQ $0x3,%YMM14,%YMM14,%YMM13	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVSD (%RAX,%R9,8),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%RCX,8),%XMM14,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%RSI,8),%XMM5,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R13,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM13,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VINSERTF128 $0x1,%XMM3,%YMM12,%YMM13	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVHPD (%RAX,%R14,8),%XMM15,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMULPD %ZMM28,%ZMM7,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VINSERTF128 $0x1,%XMM6,%YMM10,%YMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %ZMM2,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD %ZMM0,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD %ZMM26,%ZMM25,%ZMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD132PD %ZMM26,%ZMM25,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VINSERTF64X4 $0x1,%YMM9,%ZMM13,%ZMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VPADDD -0x2b0(%RBP),%ZMM1,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	1
VFMADD231PD %ZMM27,%ZMM17,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM10,%ZMM11,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM6,%ZMM15,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VPMOVSXDQ %YMM9,%ZMM14	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VEXTRACTI32X8 $0x1,%ZMM9,%YMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VPMOVSXDQ %YMM3,%ZMM11	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VEXTRACTI64X2 $0x1,%YMM14,%XMM10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VPEXTRQ $0x1,%XMM14,%RSI	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM14,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM14,%YMM14,%YMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VEXTRACTI64X4 $0x1,%ZMM14,%YMM14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VMOVQ %XMM10,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM14,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI64X2 $0x1,%YMM14,%XMM6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVQ %XMM9,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM14,%YMM14,%YMM15	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVSD (%RAX,%R13,8),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM6,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%R12,8),%XMM14,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R14,8),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R11,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM10,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R8,8),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RSI,8),%XMM10,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVQ %XMM11,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VINSERTF128 $0x1,%XMM9,%YMM3,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVHPD (%RAX,%R9,8),%XMM15,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VPEXTRQ $0x1,%XMM11,%RSI	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VINSERTF128 $0x1,%XMM9,%YMM14,%YMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VEXTRACTI64X2 $0x1,%YMM11,%XMM9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VINSERTF64X4 $0x1,%YMM6,%ZMM3,%ZMM10	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VALIGNQ $0x3,%YMM11,%YMM11,%YMM14	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VEXTRACTI64X4 $0x1,%ZMM11,%YMM11	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VMOVQ %XMM9,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM11,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM11,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI64X2 $0x1,%YMM11,%XMM6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVQ %XMM14,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM11,%YMM11,%YMM15	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVSD (%RAX,%R13,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM6,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%R12,8),%XMM11,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R11,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RAX,%R14,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%RCX,8),%XMM9,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM14,%YMM3,%YMM15	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVHPD (%RAX,%R9,8),%XMM6,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R8,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RSI,8),%XMM9,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM14,%YMM11,%YMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VPADDD -0x2f0(%RBP),%ZMM1,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	1
VMOVAPD %ZMM0,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD -0x170(%RBP),%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VINSERTF64X4 $0x1,%YMM15,%ZMM3,%ZMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VMOVAPD -0x1f0(%RBP),%ZMM19	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VPADDD -0x330(%RBP),%ZMM1,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	1
VMULPD %ZMM23,%ZMM7,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD132PD %ZMM22,%ZMM21,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMULPD %ZMM23,%ZMM8,%ZMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD231PD %ZMM24,%ZMM17,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VEXTRACTI32X8 $0x1,%ZMM11,%YMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VFMADD231PD %ZMM24,%ZMM16,%ZMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VPMOVSXDQ %YMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VADDPD %ZMM6,%ZMM15,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VPMOVSXDQ %YMM11,%ZMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VADDPD %ZMM14,%ZMM18,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VEXTRACTI64X2 $0x1,%YMM6,%XMM14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VPEXTRQ $0x1,%XMM6,%RSI	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM6,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM6,%YMM6,%YMM11	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VEXTRACTI64X4 $0x1,%ZMM6,%YMM6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VMOVQ %XMM14,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM6,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM6,%R11	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI64X2 $0x1,%YMM6,%XMM14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVQ %XMM11,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R8,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RSI,8),%XMM11,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVQ %XMM3,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM3,%RSI	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VALIGNQ $0x3,%YMM6,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVQ %XMM14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R13,8),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM6,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R12,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R11,8),%XMM6,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%R14,8),%XMM14,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM14,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVSD (%RAX,%R9,8),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM14,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM14,%YMM11,%YMM14	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VINSERTF64X4 $0x1,%YMM6,%ZMM14,%ZMM11	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VALIGNQ $0x3,%YMM3,%YMM3,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VEXTRACTI64X2 $0x1,%YMM3,%XMM14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VEXTRACTI64X4 $0x1,%ZMM3,%YMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VMOVQ %XMM6,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM3,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM3,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI64X2 $0x1,%YMM3,%XMM6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVQ %XMM14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM3,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVQ %XMM6,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R13,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RAX,%R14,8),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM3,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%RCX,8),%XMM14,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%R12,8),%XMM6,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM3,%YMM14,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVSD (%RAX,%R11,8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R9,8),%XMM3,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R8,8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RSI,8),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM14,%YMM3,%YMM14	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VINSERTF64X4 $0x1,%YMM6,%ZMM14,%ZMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VMOVAPD -0x1b0(%RBP),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD %ZMM14,%ZMM7,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMULPD %ZMM14,%ZMM8,%ZMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD231PD %ZMM20,%ZMM16,%ZMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM20,%ZMM17,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM19,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD -0xf0(%RBP),%ZMM2,%ZMM19	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD -0xf0(%RBP),%ZMM0,%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM20,-0x130(%RBP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VFMADD132PD %ZMM31,%ZMM30,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD132PD %ZMM31,%ZMM30,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM19,%ZMM14,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM20,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM14,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMULPD %ZMM11,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD231PD %ZMM18,%ZMM9,%ZMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM15,%ZMM10,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VPMOVSXDQ %YMM1,%ZMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VEXTRACTI32X8 $0x1,%ZMM1,%YMM10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VPMOVSXDQ %YMM10,%ZMM14	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VEXTRACTI64X2 $0x1,%YMM9,%XMM11	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VPEXTRQ $0x1,%XMM9,%RSI	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM9,%YMM9,%YMM10	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VEXTRACTI64X4 $0x1,%ZMM9,%YMM9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VMOVQ %XMM11,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM9,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RAX,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VEXTRACTI64X2 $0x1,%YMM9,%XMM15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVQ %XMM10,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM9,%YMM9,%YMM11	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVQ %XMM15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%R12,8),%XMM1,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R14,8),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM11,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R11,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM10,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%R9,8),%XMM11,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM9,%YMM15,%YMM10	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVSD (%RAX,%R8,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RSI,8),%XMM9,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVQ %XMM14,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VINSERTF128 $0x1,%XMM1,%YMM15,%YMM11	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VPEXTRQ $0x1,%XMM14,%RSI	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI64X2 $0x1,%YMM14,%XMM15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VINSERTF64X4 $0x1,%YMM10,%ZMM11,%ZMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VALIGNQ $0x3,%YMM14,%YMM14,%YMM11	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VEXTRACTI64X4 $0x1,%ZMM14,%YMM14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VMOVQ %XMM15,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM14,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RAX,%R13,8),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VEXTRACTI64X2 $0x1,%YMM14,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVQ %XMM11,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM14,%YMM14,%YMM15	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVQ %XMM1,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%R12,8),%XMM10,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R8,8),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RAX,%R14,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%RCX,8),%XMM11,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R11,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VINSERTF128 $0x1,%XMM14,%YMM1,%YMM15	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVHPD (%RAX,%R9,8),%XMM11,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%RSI,8),%XMM10,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVAPD -0x230(%RBP),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VINSERTF128 $0x1,%XMM14,%YMM1,%YMM11	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VINSERTF64X4 $0x1,%YMM15,%ZMM11,%ZMM14	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VMOVAPD -0x270(%RBP),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD %ZMM15,%ZMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMULPD %ZMM15,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD231PD %ZMM10,%ZMM17,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM10,%ZMM16,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM7,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM8,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM9,%ZMM0,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD132PD %ZMM13,%ZMM9,%ZMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMULPD %ZMM2,%ZMM14,%ZMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD132PD %ZMM12,%ZMM13,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM6,%ZMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD -0xb0(%RBP),%ZMM4,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM5,%ZMM3,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD -0x70(%RBP),%ZMM5,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVAPD %ZMM12,-0xb0(%RBP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVAPD %ZMM6,-0x70(%RBP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
CMP %RDX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 4300a0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x5e0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE
Source file and lines	BsplineFunctor.h:246-260
Module	exec

gain
potential
hint
expert

Vectorization

Details

53% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

17% of SSE/AVX loads are used in vector version.
57% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 160 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 2 occurrences
VMOVAPD: 3 occurrences
VPEXTRQ: 16 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 16 suboptimal vector unaligned load/store instructions.

Details

VINSERTF128: 16 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

54 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 576 FP arithmetical operations:

272: addition or subtraction (160 inside FMA instructions)
304: multiply (160 inside FMA instructions)

The binary loop is loading 1408 bytes (176 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.36 FP operations per loaded or stored byte.

General properties

nb instructions	279
nb uops	299
loop length	1720
used x86 registers	12
used mmx registers	0
used xmm registers	12
used ymm registers	12
used zmm registers	32
nb stack references	12
ADD-SUB / MUL ratio	0.78

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	49.83 cycles
front end	49.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	27.00	27.00	27.00	46.25	46.17	46.25	46.33	35.00	35.00
cycles	0.50	0.50	0.25	0.25	0.50	31.67	31.67	31.67	77.25	53.17	46.25	60.33	35.00	35.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	49.83
Dispatch	77.25
Data deps.	1.00
Overall L1	77.25

Vectorization ratios

INT

all	46%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	44%

all	59%
load	14%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	53%
load	17%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	57%

Vector efficiency ratios

INT

all	27%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	54%
load	25%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	51%

INT+FP

all	42%
load	28%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 77.25 cycles. At this rate:

18% of peak load performance is reached (18.23 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.49 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4300a0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMULPD (%RDX),%ZMM29,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0x40(%RDX),%ZMM29,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
SUB $-0x80,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VRNDSCALEPD $0xb,%ZMM12,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VCVTTPD2DQ %ZMM12,%YMM13	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	1.33
VCVTTPD2DQ %ZMM8,%YMM15	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	1.33
VPMOVSXDQ %YMM13,%ZMM10	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VPMOVSXDQ %YMM15,%ZMM14	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VINSERTI64X4 $0x1,%YMM15,%ZMM13,%ZMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VSUBPD %ZMM6,%ZMM12,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VEXTRACTI64X4 $0x1,%ZMM10,%YMM12	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VPEXTRQ $0x1,%XMM10,%RSI	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI64X2 $0x1,%YMM10,%XMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VPEXTRQ $0x1,%XMM12,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R13,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RAX,%R8,8),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R12,8),%XMM9,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMULPD %ZMM0,%ZMM0,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVQ %XMM14,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM10,%YMM10,%YMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVQ %XMM5,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMULPD %ZMM0,%ZMM7,%ZMM17	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VEXTRACTI64X2 $0x1,%YMM12,%XMM15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVQ %XMM3,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R11,8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VALIGNQ $0x3,%YMM12,%YMM12,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVQ %XMM15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%R9,8),%XMM3,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%RSI,8),%XMM13,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VPEXTRQ $0x1,%XMM14,%RSI	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VRNDSCALEPD $0xb,%ZMM8,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVQ %XMM6,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VINSERTF128 $0x1,%XMM12,%YMM15,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VSUBPD %ZMM11,%ZMM8,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVSD (%RAX,%R14,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM11,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM10,%YMM4,%YMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VEXTRACTI64X2 $0x1,%YMM14,%XMM9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VINSERTF64X4 $0x1,%YMM5,%ZMM6,%ZMM4	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VMULPD %ZMM2,%ZMM2,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVAPD %ZMM2,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD %ZMM22,%ZMM21,%ZMM18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMULPD %ZMM2,%ZMM8,%ZMM16	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VALIGNQ $0x3,%YMM14,%YMM14,%YMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VEXTRACTI64X4 $0x1,%ZMM14,%YMM14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VMOVQ %XMM9,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM14,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM14,%R11	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RAX,%R12,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R11,8),%XMM11,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMULPD %ZMM28,%ZMM8,%ZMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VEXTRACTI64X2 $0x1,%YMM14,%XMM12	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVQ %XMM5,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R8,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD231PD %ZMM27,%ZMM16,%ZMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VALIGNQ $0x3,%YMM14,%YMM14,%YMM13	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVSD (%RAX,%R9,8),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%RCX,8),%XMM14,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%RSI,8),%XMM5,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R13,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM13,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VINSERTF128 $0x1,%XMM3,%YMM12,%YMM13	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVHPD (%RAX,%R14,8),%XMM15,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMULPD %ZMM28,%ZMM7,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VINSERTF128 $0x1,%XMM6,%YMM10,%YMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %ZMM2,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD %ZMM0,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD %ZMM26,%ZMM25,%ZMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD132PD %ZMM26,%ZMM25,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VINSERTF64X4 $0x1,%YMM9,%ZMM13,%ZMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VPADDD -0x2b0(%RBP),%ZMM1,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	1
VFMADD231PD %ZMM27,%ZMM17,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM10,%ZMM11,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM6,%ZMM15,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VPMOVSXDQ %YMM9,%ZMM14	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VEXTRACTI32X8 $0x1,%ZMM9,%YMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VPMOVSXDQ %YMM3,%ZMM11	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VEXTRACTI64X2 $0x1,%YMM14,%XMM10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VPEXTRQ $0x1,%XMM14,%RSI	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM14,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM14,%YMM14,%YMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VEXTRACTI64X4 $0x1,%ZMM14,%YMM14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VMOVQ %XMM10,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM14,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI64X2 $0x1,%YMM14,%XMM6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVQ %XMM9,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM14,%YMM14,%YMM15	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVSD (%RAX,%R13,8),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM6,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%R12,8),%XMM14,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R14,8),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R11,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM10,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R8,8),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RSI,8),%XMM10,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVQ %XMM11,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VINSERTF128 $0x1,%XMM9,%YMM3,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVHPD (%RAX,%R9,8),%XMM15,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VPEXTRQ $0x1,%XMM11,%RSI	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VINSERTF128 $0x1,%XMM9,%YMM14,%YMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VEXTRACTI64X2 $0x1,%YMM11,%XMM9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VINSERTF64X4 $0x1,%YMM6,%ZMM3,%ZMM10	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VALIGNQ $0x3,%YMM11,%YMM11,%YMM14	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VEXTRACTI64X4 $0x1,%ZMM11,%YMM11	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VMOVQ %XMM9,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM11,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM11,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI64X2 $0x1,%YMM11,%XMM6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVQ %XMM14,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM11,%YMM11,%YMM15	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVSD (%RAX,%R13,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM6,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%R12,8),%XMM11,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R11,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RAX,%R14,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%RCX,8),%XMM9,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM14,%YMM3,%YMM15	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVHPD (%RAX,%R9,8),%XMM6,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R8,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RSI,8),%XMM9,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM14,%YMM11,%YMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VPADDD -0x2f0(%RBP),%ZMM1,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	1
VMOVAPD %ZMM0,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD -0x170(%RBP),%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VINSERTF64X4 $0x1,%YMM15,%ZMM3,%ZMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VMOVAPD -0x1f0(%RBP),%ZMM19	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VPADDD -0x330(%RBP),%ZMM1,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	1
VMULPD %ZMM23,%ZMM7,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD132PD %ZMM22,%ZMM21,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMULPD %ZMM23,%ZMM8,%ZMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD231PD %ZMM24,%ZMM17,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VEXTRACTI32X8 $0x1,%ZMM11,%YMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VFMADD231PD %ZMM24,%ZMM16,%ZMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VPMOVSXDQ %YMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VADDPD %ZMM6,%ZMM15,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VPMOVSXDQ %YMM11,%ZMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VADDPD %ZMM14,%ZMM18,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VEXTRACTI64X2 $0x1,%YMM6,%XMM14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VPEXTRQ $0x1,%XMM6,%RSI	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM6,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM6,%YMM6,%YMM11	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VEXTRACTI64X4 $0x1,%ZMM6,%YMM6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VMOVQ %XMM14,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM6,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM6,%R11	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI64X2 $0x1,%YMM6,%XMM14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVQ %XMM11,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R8,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RSI,8),%XMM11,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVQ %XMM3,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM3,%RSI	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VALIGNQ $0x3,%YMM6,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVQ %XMM14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R13,8),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM6,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R12,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R11,8),%XMM6,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%R14,8),%XMM14,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM14,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVSD (%RAX,%R9,8),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM14,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM14,%YMM11,%YMM14	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VINSERTF64X4 $0x1,%YMM6,%ZMM14,%ZMM11	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VALIGNQ $0x3,%YMM3,%YMM3,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VEXTRACTI64X2 $0x1,%YMM3,%XMM14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VEXTRACTI64X4 $0x1,%ZMM3,%YMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VMOVQ %XMM6,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM3,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM3,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI64X2 $0x1,%YMM3,%XMM6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVQ %XMM14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM3,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVQ %XMM6,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R13,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RAX,%R14,8),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM3,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%RCX,8),%XMM14,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%R12,8),%XMM6,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM3,%YMM14,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVSD (%RAX,%R11,8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R9,8),%XMM3,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R8,8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RSI,8),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM14,%YMM3,%YMM14	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VINSERTF64X4 $0x1,%YMM6,%ZMM14,%ZMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VMOVAPD -0x1b0(%RBP),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD %ZMM14,%ZMM7,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMULPD %ZMM14,%ZMM8,%ZMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD231PD %ZMM20,%ZMM16,%ZMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM20,%ZMM17,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM19,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD -0xf0(%RBP),%ZMM2,%ZMM19	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD -0xf0(%RBP),%ZMM0,%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM20,-0x130(%RBP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VFMADD132PD %ZMM31,%ZMM30,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD132PD %ZMM31,%ZMM30,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM19,%ZMM14,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM20,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM14,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMULPD %ZMM11,%ZMM6,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD231PD %ZMM18,%ZMM9,%ZMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM15,%ZMM10,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VPMOVSXDQ %YMM1,%ZMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VEXTRACTI32X8 $0x1,%ZMM1,%YMM10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VPMOVSXDQ %YMM10,%ZMM14	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VEXTRACTI64X2 $0x1,%YMM9,%XMM11	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VPEXTRQ $0x1,%XMM9,%RSI	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM9,%YMM9,%YMM10	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VEXTRACTI64X4 $0x1,%ZMM9,%YMM9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VMOVQ %XMM11,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM9,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RAX,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VEXTRACTI64X2 $0x1,%YMM9,%XMM15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVQ %XMM10,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM9,%YMM9,%YMM11	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVQ %XMM15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%R12,8),%XMM1,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R14,8),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM11,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RAX,%R11,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM10,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%R9,8),%XMM11,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM9,%YMM15,%YMM10	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVSD (%RAX,%R8,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RSI,8),%XMM9,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVQ %XMM14,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VINSERTF128 $0x1,%XMM1,%YMM15,%YMM11	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VPEXTRQ $0x1,%XMM14,%RSI	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI64X2 $0x1,%YMM14,%XMM15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VINSERTF64X4 $0x1,%YMM10,%ZMM11,%ZMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VALIGNQ $0x3,%YMM14,%YMM14,%YMM11	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VEXTRACTI64X4 $0x1,%ZMM14,%YMM14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VMOVQ %XMM15,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM14,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RAX,%R13,8),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VEXTRACTI64X2 $0x1,%YMM14,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VMOVQ %XMM11,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VALIGNQ $0x3,%YMM14,%YMM14,%YMM15	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50
VMOVQ %XMM1,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%R12,8),%XMM10,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R8,8),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RAX,%R14,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%RCX,8),%XMM11,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R11,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VINSERTF128 $0x1,%XMM14,%YMM1,%YMM15	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVHPD (%RAX,%R9,8),%XMM11,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%RSI,8),%XMM10,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVAPD -0x230(%RBP),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VINSERTF128 $0x1,%XMM14,%YMM1,%YMM11	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VINSERTF64X4 $0x1,%YMM15,%ZMM11,%ZMM14	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VMOVAPD -0x270(%RBP),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD %ZMM15,%ZMM7,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMULPD %ZMM15,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD231PD %ZMM10,%ZMM17,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM10,%ZMM16,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM7,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM8,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM9,%ZMM0,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD132PD %ZMM13,%ZMM9,%ZMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMULPD %ZMM2,%ZMM14,%ZMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD132PD %ZMM12,%ZMM13,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM6,%ZMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD -0xb0(%RBP),%ZMM4,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM5,%ZMM3,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD -0x70(%RBP),%ZMM5,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVAPD %ZMM12,-0xb0(%RBP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVAPD %ZMM6,-0x70(%RBP)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
CMP %RDX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 4300a0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x5e0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.45	0.05	0.3	0.05	0.18	0.05	0.07	0.06	0.03	0.05	0.01	0.04	0.01	0.03

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.04	0.07
2x2	4	0.45	0.75	1.6666666666667	0.06	0.09
2x4	8	0.3	1	3.3333333333333	0.05	0.07
2x8	16	0.18	1	5.6666666666667	0.05	0.06
2x16	32	0.07	0.75	11.333333333333	0.05	0.06
2x32	64	0.03	0.75	22	0.07	0.05
2x64	128	0.01	0.6	43.333333333333	0.08	0.04
2x96	192	0.01	0.5	64.666666666667	0.13	0.03

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency