OV - - Loop 2748

	Loop Id: 2748	Module: exec	Source: SoaDistanceTableABOMPTarget.h:228-228 [...]	Coverage: 11.26%

0x599450 VMOVSD	(%RBX,%RAX,8),%XMM1    [1]

0x599455 VMOVSD	(%RBX,%RSI,1),%XMM2    [4]

0x59945a VSUBSD	%XMM7,%XMM1,%XMM0

0x59945e VSUBSD	%XMM8,%XMM2,%XMM3

0x599463 VMULSD	%XMM26,%XMM3,%XMM2

0x599469 VFMADD231SD	%XMM27,%XMM0,%XMM2

0x59946f VMULSD	%XMM23,%XMM3,%XMM1

0x599475 VMULSD	%XMM20,%XMM3,%XMM3

0x59947b VFMADD231SD	%XMM24,%XMM0,%XMM1

0x599481 VMOVSD	(%RBX,%R9,1),%XMM4    [6]

0x599487 VSUBSD	%XMM9,%XMM4,%XMM4

0x59948c VFMADD132SD	%XMM21,%XMM3,%XMM0

0x599492 VFMADD231SD	%XMM25,%XMM4,%XMM2

0x599498 VFMADD231SD	%XMM22,%XMM4,%XMM1

0x59949e VFMADD132SD	%XMM19,%XMM0,%XMM4

0x5994a4 VMOVAPD	%XMM5,%XMM0

0x5994a8 VPTERNLOGQ	$-0x8,%XMM6,%XMM2,%XMM0

0x5994af VMOVSD	%XMM4,%XMM4,%XMM3

0x5994b3 VADDSD	%XMM0,%XMM2,%XMM4

0x5994b7 VRNDSCALESD	$0x3,%XMM4,%XMM4,%XMM0

0x5994be VSUBSD	%XMM0,%XMM2,%XMM2

0x5994c2 VMOVAPD	%XMM5,%XMM0

0x5994c6 VPTERNLOGQ	$-0x8,%XMM6,%XMM1,%XMM0

0x5994cd VADDSD	%XMM0,%XMM1,%XMM4

0x5994d1 VRNDSCALESD	$0x3,%XMM4,%XMM4,%XMM0

0x5994d8 VSUBSD	%XMM0,%XMM1,%XMM0

0x5994dc VMOVAPD	%XMM5,%XMM1

0x5994e0 VPTERNLOGQ	$-0x8,%XMM6,%XMM3,%XMM1

0x5994e7 VADDSD	%XMM1,%XMM3,%XMM4

0x5994eb VRNDSCALESD	$0x3,%XMM4,%XMM4,%XMM1

0x5994f2 VSUBSD	%XMM1,%XMM3,%XMM4

0x5994f6 VMULSD	%XMM17,%XMM0,%XMM3

0x5994fc VMULSD	%XMM14,%XMM0,%XMM1

0x599501 VFMADD231SD	%XMM18,%XMM2,%XMM3

0x599507 VFMADD231SD	%XMM15,%XMM2,%XMM1

0x59950c VMULSD	%XMM11,%XMM0,%XMM0

0x599511 VFMADD231SD	%XMM12,%XMM2,%XMM0

0x599516 VFMADD231SD	%XMM16,%XMM4,%XMM3

0x59951c VFMADD231SD	%XMM13,%XMM4,%XMM1

0x599521 VFMADD231SD	%XMM10,%XMM4,%XMM0

0x599526 VMOVSD	%XMM3,(%RCX,%RAX,8)    [2]

0x59952b VMOVSD	%XMM1,(%RCX,%RSI,1)    [5]

0x599530 VMOVSD	%XMM0,(%RCX,%R9,1)    [3]

0x599536 VMOVSD	(%RCX,%RAX,8),%XMM4    [2]

0x59953b VMOVSD	(%RCX,%RSI,1),%XMM2    [5]

0x599540 VMULSD	%XMM2,%XMM2,%XMM3

0x599544 VFMADD132SD	%XMM4,%XMM3,%XMM4

0x599549 ADD	$0x8,%RSI

0x59954d ADD	$0x8,%R9

0x599551 VFMADD132SD	%XMM0,%XMM4,%XMM0

0x599556 VSQRTSD	%XMM0,%XMM0,%XMM0

0x59955a VMOVSD	%XMM0,(%R11,%RAX,8)    [7]

0x599560 INC	%RAX

0x599563 CMP	%EAX,%R10D

0x599566 JG	599450

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h: 228 - 228

--------------------------------------------------------------------------------

228:           for (int iel = first; iel < last; iel++)

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 280 - 298

--------------------------------------------------------------------------------

280:     T displ_0 = px[iat] - x0;

281:     T displ_1 = py[iat] - y0;

282:     T displ_2 = pz[iat] - z0;

283:

284:     T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

285:     T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

286:     T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

287:

288:     //put them in the box

289:     ar_0 -= round(ar_0);

290:     ar_1 -= round(ar_1);

291:     ar_2 -= round(ar_2);

292:

293:     //unit2cart

294:     dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

295:     dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

296:     dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

297:

298:     temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.89
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.22
Bottlenecks	P8, P9,
Function	_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE
Source	SoaDistanceTableABOMPTarget.h:228-228,ParticleBConds3DSoa.h:280-298
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	3.81
CQA cycles if fully vectorized	2.75
Front-end cycles	9.00
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.50
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	11.00
P8 cycles	11.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	8.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	54.00
Nb loads	5.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	4.09
Nb FLOP add-sub	9.00
Nb FLOP mul	7.00
Nb FLOP fma	14.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.55
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	12.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	60.00
Vector-efficiency ratio all	14.00
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	20.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.89
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.22
Bottlenecks	P8, P9,
Function	_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE
Source	SoaDistanceTableABOMPTarget.h:228-228,ParticleBConds3DSoa.h:280-298
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	3.81
CQA cycles if fully vectorized	2.75
Front-end cycles	9.00
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.50
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	11.00
P8 cycles	11.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	8.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	54.00
Nb loads	5.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	4.09
Nb FLOP add-sub	9.00
Nb FLOP mul	7.00
Nb FLOP fma	14.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.55
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	12.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	60.00
Vector-efficiency ratio all	14.00
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	20.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE
Source file and lines	SoaDistanceTableABOMPTarget.h:228-228
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:228
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.00 to 2.75 cycles (4.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.00 to 9.00 cycles (1.22x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 14 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

34 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 45 FP arithmetical operations:

23: addition or subtraction (14 inside FMA instructions)
21: multiply (14 inside FMA instructions)
1: square root

The binary loop is loading 40 bytes (5 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.62 FP operations per loaded or stored byte.

General properties

nb instructions	55
nb uops	54
loop length	284
used x86 registers	7
used mmx registers	0
used xmm registers	28
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	1.00	0.75	0.75	0.50	3.00	3.00	3.00	11.00	11.00	8.00	8.00	2.00	2.00
cycles	1.00	1.00	0.75	0.75	0.50	3.00	3.00	3.00	11.00	11.00	8.00	8.00	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	8.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.00
Dispatch	11.00
DIV/SQRT	8.50
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	6%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	42%

INT+FP

all	12%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	60%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	17%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

3% of peak load performance is reached (3.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.91 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 599450

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVSD (%RBX,%RAX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RBX,%RSI,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD %XMM7,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM8,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM26,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM27,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMULSD %XMM23,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM20,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM24,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD (%RBX,%R9,1),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD %XMM9,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VFMADD132SD %XMM21,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM25,%XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM22,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD132SD %XMM19,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVAPD %XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPTERNLOGQ $-0x8,%XMM6,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVSD %XMM4,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VADDSD %XMM0,%XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VRNDSCALESD $0x3,%XMM4,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM0,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVAPD %XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPTERNLOGQ $-0x8,%XMM6,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VADDSD %XMM0,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VRNDSCALESD $0x3,%XMM4,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVAPD %XMM5,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPTERNLOGQ $-0x8,%XMM6,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VADDSD %XMM1,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VRNDSCALESD $0x3,%XMM4,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM1,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM17,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM14,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM18,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM15,%XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMULSD %XMM11,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM12,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM16,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM13,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM10,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM3,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM1,(%RCX,%RSI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM0,(%RCX,%R9,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RCX,%RAX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RCX,%RSI,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMULSD %XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD132SD %XMM4,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD $0x8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VFMADD132SD %XMM0,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VSQRTSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50
VMOVSD %XMM0,(%R11,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %EAX,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JG 599450 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x5f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE
Source file and lines	SoaDistanceTableABOMPTarget.h:228-228
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:228
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 14 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Type of elements and instruction set

34 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 45 FP arithmetical operations:

23: addition or subtraction (14 inside FMA instructions)
21: multiply (14 inside FMA instructions)
1: square root

The binary loop is loading 40 bytes (5 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.62 FP operations per loaded or stored byte.

General properties

nb instructions	55
nb uops	54
loop length	284
used x86 registers	7
used mmx registers	0
used xmm registers	28
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	1.00	0.75	0.75	0.50	3.00	3.00	3.00	11.00	11.00	8.00	8.00	2.00	2.00
cycles	1.00	1.00	0.75	0.75	0.50	3.00	3.00	3.00	11.00	11.00	8.00	8.00	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	8.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.00
Dispatch	11.00
DIV/SQRT	8.50
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	6%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	42%

INT+FP

all	12%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	60%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	17%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

3% of peak load performance is reached (3.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.91 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 599450

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVSD (%RBX,%RAX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RBX,%RSI,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD %XMM7,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM8,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM26,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM27,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMULSD %XMM23,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM20,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM24,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD (%RBX,%R9,1),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD %XMM9,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VFMADD132SD %XMM21,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM25,%XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM22,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD132SD %XMM19,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVAPD %XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPTERNLOGQ $-0x8,%XMM6,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVSD %XMM4,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VADDSD %XMM0,%XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VRNDSCALESD $0x3,%XMM4,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM0,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVAPD %XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPTERNLOGQ $-0x8,%XMM6,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VADDSD %XMM0,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VRNDSCALESD $0x3,%XMM4,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVAPD %XMM5,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPTERNLOGQ $-0x8,%XMM6,%XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VADDSD %XMM1,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VRNDSCALESD $0x3,%XMM4,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM1,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM17,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM14,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM18,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM15,%XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMULSD %XMM11,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM12,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM16,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM13,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM10,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM3,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM1,(%RCX,%RSI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM0,(%RCX,%R9,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RCX,%RAX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RCX,%RSI,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMULSD %XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD132SD %XMM4,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADD $0x8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VFMADD132SD %XMM0,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VSQRTSD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50
VMOVSD %XMM0,(%R11,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %EAX,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JG 599450 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x5f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.58	4.7	0.28	8.22	0.16	9.41	0.07	9.21	0.04	7.88	0.01	6.07	0.01	5.4

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	5.25	11.26
2x2	4	0.58	0.97	1.6666666666667	5.16	11.26
2x4	8	0.28	0.94	3.3333333333333	5.6	11.44
2x8	16	0.16	0.93	5.6666666666667	5.2	11.26
2x16	32	0.07	0.81	11.333333333333	5.39	9.92
2x32	64	0.04	0.84	22	6.04	8.19
2x64	128	0.01	0.59	43.333333333333	8.77	6.15
2x96	192	0.01	0.47	64.666666666667	11.21	5.44

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency