OV - - Loop 2422

	Loop Id: 2422	Module: exec	Source: ParticleBConds3DSoa.h:237-255	Coverage: 0.36%

0x566c20 VMOVAPD	(%R9,%RDI,1),%ZMM0    [4]

0x566c27 VMOVAPD	(%R11,%RDI,1),%ZMM13    [1]

0x566c2e VMOVAPD	(%RCX,%RDI,1),%ZMM12    [6]

0x566c35 VMOVAPD	%ZMM7,%ZMM5

0x566c3b VSUBPD	%ZMM9,%ZMM0,%ZMM4

0x566c41 VSUBPD	%ZMM10,%ZMM13,%ZMM11

0x566c47 VSUBPD	%ZMM8,%ZMM12,%ZMM15

0x566c4d VMULPD	0x168(%RBX){1to8},%ZMM4,%ZMM13    [3]

0x566c54 VMULPD	0x180(%RBX){1to8},%ZMM4,%ZMM12    [3]

0x566c5b VMULPD	0x198(%RBX){1to8},%ZMM4,%ZMM14    [3]

0x566c62 VFMADD231PD	0x160(%RBX){1to8},%ZMM11,%ZMM13    [3]

0x566c69 VFMADD231PD	0x178(%RBX){1to8},%ZMM11,%ZMM12    [3]

0x566c70 VFMADD132PD	0x190(%RBX){1to8},%ZMM14,%ZMM11    [3]

0x566c77 VMOVAPD	%ZMM7,%ZMM14

0x566c7d VFMADD231PD	0x170(%RBX){1to8},%ZMM15,%ZMM13    [3]

0x566c84 VFMADD231PD	0x188(%RBX){1to8},%ZMM15,%ZMM12    [3]

0x566c8b VFMADD132PD	0x1a0(%RBX){1to8},%ZMM11,%ZMM15    [3]

0x566c92 VPTERNLOGQ	$-0x8,%ZMM6,%ZMM13,%ZMM5

0x566c99 VADDPD	%ZMM5,%ZMM13,%ZMM0

0x566c9f VPTERNLOGQ	$-0x8,%ZMM6,%ZMM12,%ZMM14

0x566ca6 VADDPD	%ZMM14,%ZMM12,%ZMM11

0x566cac VRNDSCALEPD	$0x3,%ZMM0,%ZMM4

0x566cb3 VMOVAPD	%ZMM7,%ZMM0

0x566cb9 VPTERNLOGQ	$-0x8,%ZMM6,%ZMM15,%ZMM0

0x566cc0 VRNDSCALEPD	$0x3,%ZMM11,%ZMM5

0x566cc7 VSUBPD	%ZMM4,%ZMM13,%ZMM13

0x566ccd VADDPD	%ZMM0,%ZMM15,%ZMM4

0x566cd3 VSUBPD	%ZMM5,%ZMM12,%ZMM12

0x566cd9 VRNDSCALEPD	$0x3,%ZMM4,%ZMM14

0x566ce0 VMULPD	0x120(%RBX){1to8},%ZMM12,%ZMM11    [3]

0x566ce7 VFMADD231PD	0x118(%RBX){1to8},%ZMM13,%ZMM11    [3]

0x566cee VSUBPD	%ZMM14,%ZMM15,%ZMM15

0x566cf4 VFMADD231PD	0x128(%RBX){1to8},%ZMM15,%ZMM11    [3]

0x566cfb VMOVAPD	%ZMM11,(%R12,%RDI,1)    [2]

0x566d02 VMULPD	0x138(%RBX){1to8},%ZMM12,%ZMM5    [3]

0x566d09 VFMADD231PD	0x130(%RBX){1to8},%ZMM13,%ZMM5    [3]

0x566d10 VFMADD231PD	0x140(%RBX){1to8},%ZMM15,%ZMM5    [3]

0x566d17 VMOVAPD	%ZMM5,(%RDX,%RDI,1)    [7]

0x566d1e VMULPD	0x150(%RBX){1to8},%ZMM12,%ZMM12    [3]

0x566d25 VFMADD231PD	0x148(%RBX){1to8},%ZMM13,%ZMM12    [3]

0x566d2c VFMADD132PD	0x158(%RBX){1to8},%ZMM12,%ZMM15    [3]

0x566d33 VMOVAPD	%ZMM15,(%R13,%RDI,1)    [5]

0x566d3b VMOVAPD	(%RDX,%RDI,1),%ZMM13    [7]

0x566d42 VMOVAPD	(%R12,%RDI,1),%ZMM4    [2]

0x566d49 VMULPD	%ZMM13,%ZMM13,%ZMM0

0x566d4f VFMADD231PD	%ZMM4,%ZMM4,%ZMM0

0x566d55 VFMADD132PD	%ZMM15,%ZMM0,%ZMM15

0x566d5b VSQRTPD	%ZMM15,%ZMM14

0x566d61 VMOVAPD	%ZMM14,(%R14,%RDI,1)    [8]

0x566d68 ADD	$0x40,%RDI

0x566d6c CMP	%RSI,%RDI

0x566d6f JNE	566c20

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 237 - 255

--------------------------------------------------------------------------------

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	P8, P9,
Function	_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE4moveERKNS_11ParticleSetERKNS_10TinyVectorIdLj3EEEib
Source	ParticleBConds3DSoa.h:237-255
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.00
CQA cycles if no scalar integer	22.00
CQA cycles if FP arith vectorized	22.00
CQA cycles if fully vectorized	22.00
Front-end cycles	9.17
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	16.67
P5 cycles	16.67
P6 cycles	16.67
P7 cycles	22.00
P8 cycles	22.00
P9 cycles	12.00
P10 cycles	12.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	16.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	55.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	16.36
Nb FLOP add-sub	72.00
Nb FLOP mul	56.00
Nb FLOP fma	112.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.73
Bytes prefetched	0.00
Bytes loaded	464.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	P8, P9,
Function	_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE4moveERKNS_11ParticleSetERKNS_10TinyVectorIdLj3EEEib
Source	ParticleBConds3DSoa.h:237-255
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.00
CQA cycles if no scalar integer	22.00
CQA cycles if FP arith vectorized	22.00
CQA cycles if fully vectorized	22.00
Front-end cycles	9.17
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	16.67
P5 cycles	16.67
P6 cycles	16.67
P7 cycles	22.00
P8 cycles	22.00
P9 cycles	12.00
P10 cycles	12.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	16.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	55.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	16.36
Nb FLOP add-sub	72.00
Nb FLOP mul	56.00
Nb FLOP fma	112.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.73
Bytes prefetched	0.00
Bytes loaded	464.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE4moveERKNS_11ParticleSetERKNS_10TinyVectorIdLj3EEEib
Source file and lines	ParticleBConds3DSoa.h:237-255
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237-255.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 22.00 to 16.67 cycles (1.32x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 112 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVAPD: 4 occurrences

Type of elements and instruction set

34 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 360 FP arithmetical operations:

184: addition or subtraction (112 inside FMA instructions)
168: multiply (112 inside FMA instructions)
8: square root

The binary loop is loading 464 bytes (58 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	52
nb uops	55
loop length	341
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	13
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.17 cycles
front end	9.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	9.00	9.00	9.00	11.00	11.00	7.50	7.50	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	16.67	16.67	16.67	22.00	22.00	12.00	12.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.17
Dispatch	22.00
DIV/SQRT	16.00
Data deps.	1.00
Overall L1	22.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.00 cycles. At this rate:

21% of peak load performance is reached (21.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (11.64 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 566c20

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVAPD (%R9,%RDI,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVAPD (%R11,%RDI,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVAPD (%RCX,%RDI,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVAPD %ZMM7,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VSUBPD %ZMM9,%ZMM0,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM10,%ZMM13,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM8,%ZMM12,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD 0x168(%RBX){1to8},%ZMM4,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0x180(%RBX){1to8},%ZMM4,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0x198(%RBX){1to8},%ZMM4,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD 0x160(%RBX){1to8},%ZMM11,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x178(%RBX){1to8},%ZMM11,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD132PD 0x190(%RBX){1to8},%ZMM14,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM7,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD 0x170(%RBX){1to8},%ZMM15,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x188(%RBX){1to8},%ZMM15,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD132PD 0x1a0(%RBX){1to8},%ZMM11,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VPTERNLOGQ $-0x8,%ZMM6,%ZMM13,%ZMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VADDPD %ZMM5,%ZMM13,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VPTERNLOGQ $-0x8,%ZMM6,%ZMM12,%ZMM14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VADDPD %ZMM14,%ZMM12,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VRNDSCALEPD $0x3,%ZMM0,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVAPD %ZMM7,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPTERNLOGQ $-0x8,%ZMM6,%ZMM15,%ZMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VRNDSCALEPD $0x3,%ZMM11,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM4,%ZMM13,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM0,%ZMM15,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM5,%ZMM12,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VRNDSCALEPD $0x3,%ZMM4,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD 0x120(%RBX){1to8},%ZMM12,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD 0x118(%RBX){1to8},%ZMM13,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VSUBPD %ZMM14,%ZMM15,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD231PD 0x128(%RBX){1to8},%ZMM15,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM11,(%R12,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMULPD 0x138(%RBX){1to8},%ZMM12,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD 0x130(%RBX){1to8},%ZMM13,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x140(%RBX){1to8},%ZMM15,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM5,(%RDX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMULPD 0x150(%RBX){1to8},%ZMM12,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD 0x148(%RBX){1to8},%ZMM13,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD132PD 0x158(%RBX){1to8},%ZMM12,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM15,(%R13,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVAPD (%RDX,%RDI,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVAPD (%R12,%RDI,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD %ZMM13,%ZMM13,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD231PD %ZMM4,%ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD132PD %ZMM15,%ZMM0,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VSQRTPD %ZMM15,%ZMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	16
VMOVAPD %ZMM14,(%R14,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
ADD $0x40,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RSI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 566c20 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE4moveERKNS_11ParticleSetERKNS_10TinyVectorIdLj3EEEib+0x9b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE4moveERKNS_11ParticleSetERKNS_10TinyVectorIdLj3EEEib
Source file and lines	ParticleBConds3DSoa.h:237-255
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 112 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVAPD: 4 occurrences

Type of elements and instruction set

34 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 360 FP arithmetical operations:

184: addition or subtraction (112 inside FMA instructions)
168: multiply (112 inside FMA instructions)
8: square root

The binary loop is loading 464 bytes (58 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	52
nb uops	55
loop length	341
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	13
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.17 cycles
front end	9.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	9.00	9.00	9.00	11.00	11.00	7.50	7.50	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	16.67	16.67	16.67	22.00	22.00	12.00	12.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.17
Dispatch	22.00
DIV/SQRT	16.00
Data deps.	1.00
Overall L1	22.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.00 cycles. At this rate:

21% of peak load performance is reached (21.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (11.64 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 566c20

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVAPD (%R9,%RDI,1),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVAPD (%R11,%RDI,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVAPD (%RCX,%RDI,1),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVAPD %ZMM7,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VSUBPD %ZMM9,%ZMM0,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM10,%ZMM13,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM8,%ZMM12,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD 0x168(%RBX){1to8},%ZMM4,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0x180(%RBX){1to8},%ZMM4,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0x198(%RBX){1to8},%ZMM4,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD 0x160(%RBX){1to8},%ZMM11,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x178(%RBX){1to8},%ZMM11,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD132PD 0x190(%RBX){1to8},%ZMM14,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM7,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD 0x170(%RBX){1to8},%ZMM15,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x188(%RBX){1to8},%ZMM15,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD132PD 0x1a0(%RBX){1to8},%ZMM11,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VPTERNLOGQ $-0x8,%ZMM6,%ZMM13,%ZMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VADDPD %ZMM5,%ZMM13,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VPTERNLOGQ $-0x8,%ZMM6,%ZMM12,%ZMM14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VADDPD %ZMM14,%ZMM12,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VRNDSCALEPD $0x3,%ZMM0,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVAPD %ZMM7,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPTERNLOGQ $-0x8,%ZMM6,%ZMM15,%ZMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VRNDSCALEPD $0x3,%ZMM11,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM4,%ZMM13,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM0,%ZMM15,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM5,%ZMM12,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VRNDSCALEPD $0x3,%ZMM4,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD 0x120(%RBX){1to8},%ZMM12,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD 0x118(%RBX){1to8},%ZMM13,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VSUBPD %ZMM14,%ZMM15,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD231PD 0x128(%RBX){1to8},%ZMM15,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM11,(%R12,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMULPD 0x138(%RBX){1to8},%ZMM12,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD 0x130(%RBX){1to8},%ZMM13,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x140(%RBX){1to8},%ZMM15,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM5,(%RDX,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMULPD 0x150(%RBX){1to8},%ZMM12,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD 0x148(%RBX){1to8},%ZMM13,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD132PD 0x158(%RBX){1to8},%ZMM12,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM15,(%R13,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVAPD (%RDX,%RDI,1),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVAPD (%R12,%RDI,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD %ZMM13,%ZMM13,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD231PD %ZMM4,%ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD132PD %ZMM15,%ZMM0,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VSQRTPD %ZMM15,%ZMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	16
VMOVAPD %ZMM14,(%R14,%RDI,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
ADD $0x40,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RSI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 566c20 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE4moveERKNS_11ParticleSetERKNS_10TinyVectorIdLj3EEEib+0x9b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.48	0.22	0.21	0.37	0.13	0.37	0.05	0.38	0.03	0.31	0.01	0.22	0.01	0.22

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.2	0.36
2x2	4	0.48	0.8	1.6666666666667	0.23	0.43
2x4	8	0.21	0.7	3.3333333333333	0.25	0.47
2x8	16	0.13	0.76	5.6666666666667	0.28	0.43
2x16	32	0.05	0.62	11.333333333333	0.4	0.4
2x32	64	0.03	0.67	22	0.32	0.32
2x64	128	0.01	0.5	43.333333333333	0.55	0.22
2x96	192	0.01	0.36	64.666666666667	0.63	0.22

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency