OV - - Loop 1005

	Loop Id: 1005	Module: exec	Source: inner_product.hpp:211-212	Coverage: 0.27%

0x497c7a VMOVSD	(%RAX),%XMM14    [5]

0x497c7e VMOVHPD	(%RAX,%RCX,8),%XMM14,%XMM15    [1]

0x497c83 ADD	%R9,%RAX

0x497c86 SUB	$-0x80,%RDX

0x497c8a VMOVSD	(%RAX),%XMM0    [6]

0x497c8e VMOVHPD	(%RAX,%RCX,8),%XMM0,%XMM1    [2]

0x497c93 ADD	%R9,%RAX

0x497c96 VMOVUPD	%XMM15,-0x80(%RDX)    [3]

0x497c9b VMOVSD	(%RAX),%XMM2    [17]

0x497c9f VMOVHPD	(%RAX,%RCX,8),%XMM2,%XMM3    [9]

0x497ca4 ADD	%R9,%RAX

0x497ca7 VMOVUPD	%XMM1,-0x70(%RDX)    [3]

0x497cac VMOVSD	(%RAX),%XMM4    [7]

0x497cb0 VMOVHPD	(%RAX,%RCX,8),%XMM4,%XMM5    [15]

0x497cb5 ADD	%R9,%RAX

0x497cb8 VMOVUPD	%XMM3,-0x60(%RDX)    [3]

0x497cbd VMOVSD	(%RAX),%XMM6    [12]

0x497cc1 VMOVHPD	(%RAX,%RCX,8),%XMM6,%XMM7    [14]

0x497cc6 ADD	%R9,%RAX

0x497cc9 VMOVUPD	%XMM5,-0x50(%RDX)    [3]

0x497cce VMOVSD	(%RAX),%XMM8    [10]

0x497cd2 VMOVHPD	(%RAX,%RCX,8),%XMM8,%XMM9    [11]

0x497cd7 ADD	%R9,%RAX

0x497cda VMOVUPD	%XMM7,-0x40(%RDX)    [3]

0x497cdf VMOVSD	(%RAX),%XMM10    [4]

0x497ce3 VMOVHPD	(%RAX,%RCX,8),%XMM10,%XMM11    [16]

0x497ce8 ADD	%R9,%RAX

0x497ceb VMOVUPD	%XMM9,-0x30(%RDX)    [3]

0x497cf0 VMOVSD	(%RAX),%XMM12    [8]

0x497cf4 VMOVHPD	(%RAX,%RCX,8),%XMM12,%XMM13    [13]

0x497cf9 VMOVUPD	%XMM11,-0x20(%RDX)    [3]

0x497cfe ADD	%R9,%RAX

0x497d01 VMOVUPD	%XMM13,-0x10(%RDX)    [3]

0x497d06 CMP	%R12,%RDX

0x497d09 JNE	497c7a

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 211 - 212

--------------------------------------------------------------------------------

211:     for (size_t j = 0; j < m; ++j)

212:       B[i * ldb + j] = A[j * lda + i];

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks
Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10invertPsiMERKNS1_6MatrixIdSaIdEEERS7_
Source	inner_product.hpp:211-212
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.00
Front-end cycles	5.67
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	0.50
P4 cycles	8.00
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	0.00
P8 cycles	2.67
P9 cycles	2.67
P10 cycles	2.67
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	34.00
Nb loads	16.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	33.33
Vectorization ratio load	0.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	16.67
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks
Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10invertPsiMERKNS1_6MatrixIdSaIdEEERS7_
Source	inner_product.hpp:211-212
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.00
Front-end cycles	5.67
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	0.50
P4 cycles	8.00
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	0.00
P8 cycles	2.67
P9 cycles	2.67
P10 cycles	2.67
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	34.00
Nb loads	16.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	33.33
Vectorization ratio load	0.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	16.67
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10invertPsiMERKNS1_6MatrixIdSaIdEEERS7_
Source file and lines	inner_product.hpp:211-212
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:211-212.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 8.00 to 2.00 cycles (4.00x speedup).

Details

33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 128 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	35
nb uops	34
loop length	149
used x86 registers	5
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.50	2.50	2.25	2.25	0.50	8.00	8.00	8.00	0.00	2.67	2.67	2.67	4.00	4.00
cycles	2.50	2.50	2.25	2.25	0.50	8.00	8.00	8.00	0.00	2.67	2.67	2.67	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	5.67
Dispatch	8.00
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	33%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	16%
load	12%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (16.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 497c7a

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVSD (%RAX),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM14,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB $-0x80,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RAX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %XMM15,-0x80(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD (%RAX),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM2,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %XMM1,-0x70(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD (%RAX),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM4,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %XMM3,-0x60(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD (%RAX),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM6,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %XMM5,-0x50(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD (%RAX),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM8,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %XMM7,-0x40(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD (%RAX),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM10,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %XMM9,-0x30(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD (%RAX),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM12,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
VMOVUPD %XMM11,-0x20(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %XMM13,-0x10(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
CMP %R12,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
JNE 497c7a <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10invertPsiMERKNS1_6MatrixIdSaIdEEERS7_+0x1ca>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10invertPsiMERKNS1_6MatrixIdSaIdEEERS7_
Source file and lines	inner_product.hpp:211-212
Module	exec

gain
potential
hint
expert

Vectorization

Details

33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 128 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	35
nb uops	34
loop length	149
used x86 registers	5
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.50	2.50	2.25	2.25	0.50	8.00	8.00	8.00	0.00	2.67	2.67	2.67	4.00	4.00
cycles	2.50	2.50	2.25	2.25	0.50	8.00	8.00	8.00	0.00	2.67	2.67	2.67	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	5.67
Dispatch	8.00
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	33%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	16%
load	12%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (16.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 497c7a

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVSD (%RAX),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM14,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB $-0x80,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RAX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %XMM15,-0x80(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD (%RAX),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM2,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %XMM1,-0x70(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD (%RAX),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM4,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %XMM3,-0x60(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD (%RAX),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM6,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %XMM5,-0x50(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD (%RAX),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM8,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %XMM7,-0x40(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD (%RAX),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM10,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %XMM9,-0x30(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD (%RAX),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RCX,8),%XMM12,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
VMOVUPD %XMM11,-0x20(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %XMM13,-0x10(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
CMP %R12,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
JNE 497c7a <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10invertPsiMERKNS1_6MatrixIdSaIdEEERS7_+0x1ca>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.6	0.11	0.28	0.21	0.16	0.23	0.07	0.22	0.04	0.18	0.02	0.13	0.01	0.16

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.13	0.27
2x2	4	0.6	1	1.6666666666667	0.13	0.28
2x4	8	0.28	0.93	3.3333333333333	0.13	0.29
2x8	16	0.16	0.93	5.6666666666667	0.13	0.28
2x16	32	0.07	0.81	11.333333333333	0.14	0.24
2x32	64	0.04	0.93	22	0.14	0.19
2x64	128	0.02	0.72	43.333333333333	0.36	0.13
2x96	192	0.01	0.39	64.666666666667	1.06	0.16

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency