OV - - Function _ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS

	Function: _ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEEb	Module: exec	Source: ParticleSet.cpp:264-344 [...]	Coverage: 0.01%

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h: 85 - 85

--------------------------------------------------------------------------------

85:       ret[d] = op(lhs[d], rhs[d]);

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/refwrap.h: 347 - 347

--------------------------------------------------------------------------------

347:       { return *_M_data; }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 223

--------------------------------------------------------------------------------

223:     return X[i];

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.cpp: 264 - 344

--------------------------------------------------------------------------------

264: {

265:   active_ptcl_     = iat;

266:   active_pos_      = R[iat] + displ;

267:   active_spin_val_ = spins[iat];

268:   computeNewPosDistTables(iat, active_pos_, maybe_accept);

269: }

[...]

343:   for (int i = 0; i < DistTables.size(); ++i)

344:     DistTables[i]->move(*this, newpos, iat, maybe_accept);

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h: 990 - 990

--------------------------------------------------------------------------------

990:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 43 - 43

--------------------------------------------------------------------------------

43:     return (a + b);

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/unique_ptr.h: 199 - 199

--------------------------------------------------------------------------------

199:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

0x4befa0 PUSH	%RBP

0x4befa1 MOVSXD	%ESI,%RAX

0x4befa4 MOV	%RSP,%RBP

0x4befa7 PUSH	%R15

0x4befa9 PUSH	%R14

0x4befab PUSH	%R13

0x4befad PUSH	%R12

0x4befaf PUSH	%RBX

0x4befb0 MOV	%ECX,%R13D

0x4befb3 LEA	(%RAX,%RAX,2),%RSI

0x4befb7 SUB	$0x38,%RSP

0x4befbb MOV	0x40(%RDI),%RCX

0x4befbf VMOVSD	0x10(%RDX),%XMM1

0x4befc4 MOV	0x68(%RDI),%R9

0x4befc8 MOV	%RDI,%RBX

0x4befcb MOV	%EAX,0x124(%RDI)

0x4befd1 MOV	%RAX,%R14

0x4befd4 LEA	0x128(%RBX),%R15

0x4befdb MOVZX	%R13B,%R13D

0x4befdf XOR	%R12D,%R12D

0x4befe2 LEA	(%RCX,%RSI,8),%R8

0x4befe6 VMOVUPD	(%R8),%XMM2

0x4befeb VADDPD	(%RDX),%XMM2,%XMM0

0x4befef VADDSD	0x10(%R8),%XMM1,%XMM3

0x4beff5 VMOVSD	%XMM3,-0x40(%RBP)

0x4beffa MOV	-0x40(%RBP),%RDX

0x4beffe MOV	%RDX,0x138(%RDI)

0x4bf005 VMOVDQU	%XMM0,0x128(%RDI)

0x4bf00d VMOVSD	(%R9,%RAX,8),%XMM4

0x4bf013 VMOVSD	%XMM4,0x140(%RDI)

0x4bf01b MOV	0x210(%RDI),%RDI

0x4bf022 VMOVAPD	%XMM0,-0x50(%RBP)

0x4bf027 MOV	(%RDI),%RDI

0x4bf02a MOV	%RDI,-0x58(%RBP)

0x4bf02e CALL	51ed20 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x4bf033 MOV	0x1e0(%RBX),%R11

0x4bf03a CMP	%R11,0x1e8(%RBX)

0x4bf041 JE	4bf084

0x4bf043 NOPW	%CS:(%RAX,%RAX,1)

0x4bf04e XCHG	%AX,%AX

(1245) 0x4bf050 MOV	(%R11,%R12,8),%RDI

(1245) 0x4bf054 MOV	%R13D,%R8D

(1245) 0x4bf057 MOV	%R14D,%ECX

(1245) 0x4bf05a MOV	%R15,%RDX

(1245) 0x4bf05d MOV	%RBX,%RSI

(1245) 0x4bf060 MOV	(%RDI),%R10

(1245) 0x4bf063 CALLQ	0x28(%R10)

(1245) 0x4bf067 MOV	0x1e0(%RBX),%R11

(1245) 0x4bf06e MOV	0x1e8(%RBX),%RAX

(1245) 0x4bf075 INC	%R12

(1245) 0x4bf078 SUB	%R11,%RAX

(1245) 0x4bf07b SAR	$0x3,%RAX

(1245) 0x4bf07f CMP	%RAX,%R12

(1245) 0x4bf082 JB	4bf050

0x4bf084 MOV	-0x58(%RBP),%RDI

0x4bf088 CALL	51ef50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x4bf08d ADD	$0x38,%RSP

0x4bf091 POP	%RBX

0x4bf092 POP	%R12

0x4bf094 POP	%R13

0x4bf096 POP	%R14

0x4bf098 POP	%R15

0x4bf09a POP	%RBP

0x4bf09b RET

0x4bf09c MOV	%RAX,%RBX

0x4bf09f JMP	4062c6

0x4bf0a4 NOPW	%CS:(%RAX,%RAX,1)

0x4bf0af NOP

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ParticleSet.cpp:264-344
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h:85
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/refwrap.h:347
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.cpp:264-269,343-344
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:990
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/unique_ptr.h:199

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.67 to 3.00 cycles (2.89x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 8.67 to 1.65 cycles (5.27x speedup).

Details

23% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
28% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv: 1 occurrences
_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv: 1 occurrences

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary function is loading 120 bytes (15 double precision FP elements). The binary function is storing 68 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	54
nb uops	52
loop length	220
used x86 registers	15
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.75	2.75	2.50	2.50	2.50	7.33	7.33	7.33	0.00	0.00	1.00	1.00	2.00	2.00
cycles	2.75	2.75	2.50	2.50	2.50	7.33	7.33	7.33	0.00	0.00	1.00	1.00	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.67
Dispatch	7.33
Overall L1	8.67

Vectorization ratios

INT

all	11%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	37%
load	40%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	23%
load	28%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	12%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	17%
load	17%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	16%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.67 cycles. At this rate:

14% of peak load performance is reached (13.85 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (7.85 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.67 to 7.33 cycles (1.18x speedup).

ASM code

In the binary file, the address of the function is: 4befa0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVSXD %ESI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %ECX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%RAX,%RAX,2),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SUB $0x38,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV 0x40(%RDI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD 0x10(%RDX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MOV 0x68(%RDI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EAX,0x124(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA 0x128(%RBX),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVZX %R13B,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
LEA (%RCX,%RSI,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD (%R8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
VADDPD (%RDX),%XMM2,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VADDSD 0x10(%R8),%XMM1,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM3,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
MOV -0x40(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %RDX,0x138(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
VMOVDQU %XMM0,0x128(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
VMOVSD (%R9,%RAX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD %XMM4,0x140(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
MOV 0x210(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVAPD %XMM0,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOV (%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %RDI,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
CALL 51ed20 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x1e0(%RBX),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CMP %R11,0x1e8(%RBX)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
JE 4bf084 <_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEEb+0xe4>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV -0x58(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CALL 51ef50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
ADD $0x38,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 4062c6 <_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEEb.cold>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	ParticleSet.cpp:264-344
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h:85
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/refwrap.h:347
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.cpp:264-269,343-344
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:990
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/unique_ptr.h:199

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.67 to 3.00 cycles (2.89x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

23% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
28% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv: 1 occurrences
_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv: 1 occurrences

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary function is loading 120 bytes (15 double precision FP elements). The binary function is storing 68 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	54
nb uops	52
loop length	220
used x86 registers	15
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.75	2.75	2.50	2.50	2.50	7.33	7.33	7.33	0.00	0.00	1.00	1.00	2.00	2.00
cycles	2.75	2.75	2.50	2.50	2.50	7.33	7.33	7.33	0.00	0.00	1.00	1.00	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.67
Dispatch	7.33
Overall L1	8.67

Vectorization ratios

INT

all	11%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	37%
load	40%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	23%
load	28%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	12%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	17%
load	17%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	16%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.67 cycles. At this rate:

14% of peak load performance is reached (13.85 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (7.85 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4befa0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVSXD %ESI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %ECX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%RAX,%RAX,2),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SUB $0x38,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV 0x40(%RDI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD 0x10(%RDX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MOV 0x68(%RDI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EAX,0x124(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA 0x128(%RBX),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVZX %R13B,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
LEA (%RCX,%RSI,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD (%R8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
VADDPD (%RDX),%XMM2,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VADDSD 0x10(%R8),%XMM1,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VMOVSD %XMM3,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
MOV -0x40(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %RDX,0x138(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
VMOVDQU %XMM0,0x128(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
VMOVSD (%R9,%RAX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD %XMM4,0x140(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
MOV 0x210(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVAPD %XMM0,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOV (%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %RDI,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
CALL 51ed20 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x1e0(%RBX),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CMP %R11,0x1e8(%RBX)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
JE 4bf084 <_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEEb+0xe4>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV -0x58(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CALL 51ef50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
ADD $0x38,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 4062c6 <_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEEb.cold>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	1	0	1	0	1	0	1	0	0	0	0	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	1	1	1	1	0	0.01
2x2	4	1	1	1.6666666666667	0	0
2x4	6	1	1	3.3333333333333	0	0
2x8	14	1	1	5.6666666666667	0.01	0.01
2x16	29	1	1	11.333333333333	0.01	0
2x32	58	1	1	22	0.01	0
2x64	122	0	0	43.333333333333	0.02	0
2x96	182	0	0	64.666666666667	0.02	0

Name	Coverage (%)	Time (s)
▼_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEEb–	0.01	0
○Loop 1245 - stl_vector.h:990-990 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency