OV - - Function _ZN11qmcplusplus12WaveFunction10acceptMoveERNS

	Function: _ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi	Module: exec	Source: WaveFunction.cpp:219-230 [...]	Coverage: 0.01%

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/refwrap.h: 347 - 347

--------------------------------------------------------------------------------

347:       { return *_M_data; }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp: 219 - 230

--------------------------------------------------------------------------------

219: {

220:   if (iat < nelup)

221:     Det_up->acceptMove(P, iat);

222:   else

223:     Det_dn->acceptMove(P, iat);

224:

225:   for (size_t i = 0; i < Jastrows.size(); i++)

226:   {

227:     ScopedTimer local_timer(jastrow_timers[i]);

228:     Jastrows[i]->acceptMove(P, iat);

229:   }

230: }

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h: 990 - 990

--------------------------------------------------------------------------------

990:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

0x418650 PUSH	%RBP

0x418651 MOV	%RSP,%RBP

0x418654 PUSH	%R15

0x418656 PUSH	%R14

0x418658 PUSH	%R13

0x41865a PUSH	%R12

0x41865c PUSH	%RBX

0x41865d MOV	%EDX,%R13D

0x418660 MOV	%RDI,%RBX

0x418663 SUB	$0x18,%RSP

0x418667 MOV	%RSI,-0x38(%RBP)

0x41866b CMP	%EDX,0x34(%RDI)

0x41866e JLE	4186f0

0x418674 MOV	(%RDI),%RDI

0x418677 MOV	(%RDI),%RCX

0x41867a CALLQ	0x28(%RCX)

0x41867d MOV	0x10(%RBX),%RDX

0x418681 XOR	%R12D,%R12D

0x418684 CMP	%RDX,0x18(%RBX)

0x418688 JE	4186da

0x41868a NOPW	(%RAX,%RAX,1)

(174) 0x418690 MOV	0x58(%RBX),%RSI

(174) 0x418694 LEA	(,%R12,8),%R14

(174) 0x41869c MOV	(%RSI,%R14,1),%R15

(174) 0x4186a0 MOV	%R15,%RDI

(174) 0x4186a3 CALL	51ed20 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

(174) 0x4186a8 MOV	0x10(%RBX),%RDI

(174) 0x4186ac MOV	-0x38(%RBP),%RSI

(174) 0x4186b0 MOV	%R13D,%EDX

(174) 0x4186b3 MOV	(%RDI,%R14,1),%RDI

(174) 0x4186b7 MOV	(%RDI),%R8

(174) 0x4186ba CALLQ	0x28(%R8)

(174) 0x4186be MOV	%R15,%RDI

(174) 0x4186c1 INC	%R12

(174) 0x4186c4 CALL	51ef50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

(174) 0x4186c9 MOV	0x18(%RBX),%R9

(174) 0x4186cd SUB	0x10(%RBX),%R9

(174) 0x4186d1 SAR	$0x3,%R9

(174) 0x4186d5 CMP	%R9,%R12

(174) 0x4186d8 JB	418690

0x4186da ADD	$0x18,%RSP

0x4186de POP	%RBX

0x4186df POP	%R12

0x4186e1 POP	%R13

0x4186e3 POP	%R14

0x4186e5 POP	%R15

0x4186e7 POP	%RBP

0x4186e8 RET

0x4186e9 NOPL	(%RAX)

0x4186f0 MOV	0x8(%RDI),%RDI

0x4186f4 MOV	(%RDI),%RAX

0x4186f7 CALLQ	0x28(%RAX)

0x4186fa JMP	41867d

0x4186ff MOV	%RAX,%RBX

0x418702 JMP	405008

0x418707 NOP

0x418708 NOPL	(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	WaveFunction.cpp:219-230
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/refwrap.h:347
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:219-230
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:990

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.67 to 0.92 cycles (7.27x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	38
nb uops	40
loop length	118
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.67 cycles
front end	6.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.50	1.50	1.25	1.25	3.50	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.50	1.50	1.25	1.25	3.50	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.67
Dispatch	4.00
Overall L1	6.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.67 cycles. At this rate:

10% of peak load performance is reached (10.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.20 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.67 to 4.00 cycles (1.67x speedup).

ASM code

In the binary file, the address of the function is: 418650

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
MOV %EDX,%R13D	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
CMP %EDX,0x34(%RDI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JLE 4186f0 <_ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi+0xa0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV (%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV (%RDI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CALLQ 0x28(%RCX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	2.20
MOV 0x10(%RBX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0.25
CMP %RDX,0x18(%RBX)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JE 4186da <_ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi+0x8a>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0x8(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV (%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CALLQ 0x28(%RAX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	2.20
JMP 41867d <_ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi+0x2d>	1	0.50	0	0	0	0.50	0	0	0	0	1
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
JMP 405008 <_ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi.cold>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOP	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	WaveFunction.cpp:219-230
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/refwrap.h:347
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:219-230
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:990

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	38
nb uops	40
loop length	118
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.67 cycles
front end	6.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.50	1.50	1.25	1.25	3.50	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.50	1.50	1.25	1.25	3.50	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.67
Dispatch	4.00
Overall L1	6.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.67 cycles. At this rate:

10% of peak load performance is reached (10.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.20 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 418650

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
MOV %EDX,%R13D	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
CMP %EDX,0x34(%RDI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JLE 4186f0 <_ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi+0xa0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV (%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV (%RDI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CALLQ 0x28(%RCX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	2.20
MOV 0x10(%RBX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0.25
CMP %RDX,0x18(%RBX)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JE 4186da <_ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi+0x8a>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0x8(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV (%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CALLQ 0x28(%RAX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	2.20
JMP 41867d <_ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi+0x2d>	1	0.50	0	0	0	0.50	0	0	0	0	1
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
JMP 405008 <_ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi.cold>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOP	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	1	1	1	1	0	0.01
2x2	3	1	1	1.6666666666667	0	0
2x4	3	1	1	3.3333333333333	0	0
2x8	10	1	1	5.6666666666667	0	0
2x16	21	1	1	11.333333333333	0	0
2x32	45	1	1	22	0	0
2x64	82	1	1	43.333333333333	0.01	0
2x96	130	1	1	64.666666666667	0.02	0

Name	Coverage (%)	Time (s)
▼_ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi–	0.01	0
○Loop 174 - stl_vector.h:990-990 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency