OV - - Function _ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS

	Function: _ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE	Module: exec	Source: WaveFunction.cpp:194-204 [...]	Coverage: 0.01%

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/refwrap.h: 347 - 347

--------------------------------------------------------------------------------

347:       { return *_M_data; }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 164 - 164

--------------------------------------------------------------------------------

164:       X[d] = rhs;

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp: 194 - 204

--------------------------------------------------------------------------------

194: {

195:   grad       = valT(0);

196:   valT ratio = (iat < nelup ? Det_up->ratioGrad(P, iat, grad) : Det_dn->ratioGrad(P, iat, grad));

197:

198:   for (size_t i = 0; i < Jastrows.size(); i++)

199:   {

200:     ScopedTimer local_timer(jastrow_timers[i]);

201:     ratio *= Jastrows[i]->ratioGrad(P, iat, grad);

202:   }

203:   return ratio;

204: }

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h: 990 - 990

--------------------------------------------------------------------------------

990:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

0x418490 PUSH	%RBP

0x418491 MOV	%RSP,%RBP

0x418494 PUSH	%R15

0x418496 PUSH	%R14

0x418498 PUSH	%R13

0x41849a PUSH	%R12

0x41849c PUSH	%RBX

0x41849d MOV	%RCX,%R14

0x4184a0 MOV	%RDI,%RBX

0x4184a3 SUB	$0x28,%RSP

0x4184a7 MOV	%RSI,-0x40(%RBP)

0x4184ab MOV	%EDX,-0x44(%RBP)

0x4184ae MOVQ	$0,(%RCX)

0x4184b5 MOVQ	$0,0x8(%RCX)

0x4184bd MOVQ	$0,0x10(%RCX)

0x4184c5 CMP	%EDX,0x34(%RDI)

0x4184c8 JLE	418560

0x4184ce MOV	(%RDI),%RDI

0x4184d1 MOV	(%RDI),%R8

0x4184d4 CALLQ	0x20(%R8)

0x4184d8 VMOVSD	%XMM0,-0x38(%RBP)

0x4184dd MOV	0x10(%RBX),%RDX

0x4184e1 XOR	%R12D,%R12D

0x4184e4 CMP	%RDX,0x18(%RBX)

0x4184e8 JE	418547

0x4184ea NOPW	(%RAX,%RAX,1)

(172) 0x4184f0 MOV	0x58(%RBX),%RCX

(172) 0x4184f4 LEA	(,%R12,8),%R15

(172) 0x4184fc MOV	(%RCX,%R15,1),%R13

(172) 0x418500 MOV	%R13,%RDI

(172) 0x418503 CALL	51ed20 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

(172) 0x418508 MOV	0x10(%RBX),%RSI

(172) 0x41850c MOV	-0x44(%RBP),%EDX

(172) 0x41850f MOV	%R14,%RCX

(172) 0x418512 MOV	(%RSI,%R15,1),%RDI

(172) 0x418516 MOV	-0x40(%RBP),%RSI

(172) 0x41851a MOV	(%RDI),%R9

(172) 0x41851d CALLQ	0x20(%R9)

(172) 0x418521 MOV	%R13,%RDI

(172) 0x418524 VMULSD	-0x38(%RBP),%XMM0,%XMM1

(172) 0x418529 VMOVSD	%XMM1,-0x38(%RBP)

(172) 0x41852e INC	%R12

(172) 0x418531 CALL	51ef50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

(172) 0x418536 MOV	0x18(%RBX),%RDI

(172) 0x41853a SUB	0x10(%RBX),%RDI

(172) 0x41853e SAR	$0x3,%RDI

(172) 0x418542 CMP	%RDI,%R12

(172) 0x418545 JB	4184f0

0x418547 VMOVSD	-0x38(%RBP),%XMM0

0x41854c ADD	$0x28,%RSP

0x418550 POP	%RBX

0x418551 POP	%R12

0x418553 POP	%R13

0x418555 POP	%R14

0x418557 POP	%R15

0x418559 POP	%RBP

0x41855a RET

0x41855b NOPL	(%RAX,%RAX,1)

0x418560 MOV	0x8(%RDI),%RDI

0x418564 MOV	(%RDI),%RAX

0x418567 CALLQ	0x20(%RAX)

0x41856a VMOVSD	%XMM0,-0x38(%RBP)

0x41856f JMP	4184dd

0x418574 MOV	%RAX,%RBX

0x418577 JMP	404fe0

0x41857c NOPL	(%RAX)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	WaveFunction.cpp:194-204
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/refwrap.h:347
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:164
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:194-204
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:990

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.83 to 1.17 cycles (6.71x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 7.83 to 1.17 cycles (6.71x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	44
nb uops	47
loop length	153
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.83 cycles
front end	7.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.50	1.50	1.25	1.25	3.50	6.33	6.33	6.33	0.00	0.00	0.00	0.00	1.00	1.00
cycles	3.50	1.50	1.25	1.25	3.50	6.33	6.33	6.33	0.00	0.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.83
Dispatch	6.33
Overall L1	7.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	8%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	10%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.83 cycles. At this rate:

10% of peak load performance is reached (9.70 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (6.64 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.83 to 6.33 cycles (1.24x speedup).

ASM code

In the binary file, the address of the function is: 418490

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RSI,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %EDX,-0x44(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVQ $0,(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVQ $0,0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVQ $0,0x10(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CMP %EDX,0x34(%RDI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JLE 418560 <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE+0xd0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV (%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RDI),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CALLQ 0x20(%R8)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	0	0	2.20
VMOVSD %XMM0,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOV 0x10(%RBX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.25
CMP %RDX,0x18(%RBX)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JE 418547 <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE+0xb7>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VMOVSD -0x38(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0x8(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CALLQ 0x20(%RAX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	0	0	2.20
VMOVSD %XMM0,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
JMP 4184dd <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE+0x4d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 404fe0 <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE.cold>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	WaveFunction.cpp:194-204
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/refwrap.h:347
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:164
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:194-204
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:990

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.83 to 1.17 cycles (6.71x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	44
nb uops	47
loop length	153
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.83 cycles
front end	7.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.50	1.50	1.25	1.25	3.50	6.33	6.33	6.33	0.00	0.00	0.00	0.00	1.00	1.00
cycles	3.50	1.50	1.25	1.25	3.50	6.33	6.33	6.33	0.00	0.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.83
Dispatch	6.33
Overall L1	7.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	8%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	10%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.83 cycles. At this rate:

10% of peak load performance is reached (9.70 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (6.64 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 418490

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RSI,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %EDX,-0x44(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVQ $0,(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVQ $0,0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVQ $0,0x10(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CMP %EDX,0x34(%RDI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JLE 418560 <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE+0xd0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV (%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RDI),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CALLQ 0x20(%R8)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	0	0	2.20
VMOVSD %XMM0,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOV 0x10(%RBX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.25
CMP %RDX,0x18(%RBX)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JE 418547 <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE+0xb7>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VMOVSD -0x38(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0x8(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CALLQ 0x20(%RAX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	0	0	2.20
VMOVSD %XMM0,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
JMP 4184dd <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE+0x4d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 404fe0 <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE.cold>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 2Number nodes: 1Number processes per node: 2Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -np <number_processes>Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/run/oneview_runs/compilers/gcc_2/oneview_run_1708580749I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	1	0	1	0	1	0	1	0	1	0	0	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0	0.01
2x2	3	1	1	1.6666666666667	0	0
2x4	7	1	1	3.3333333333333	0	0
2x8	16	1	1	5.6666666666667	0.01	0.01
2x16	31	1	1	11.333333333333	0.01	0
2x32	61	1	1	22	0.01	0
2x64	127	1	1	43.333333333333	0.01	0
2x96	192	0	0	64.666666666667	0.03	0

Name	Coverage (%)	Time (s)
▼_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE–	0.01	0
○Loop 172 - stl_vector.h:990-990 - exec	0.01	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency