OV - exec - Loop 832

	Loop Id: 832	Module: exec	Source: inner_product.hpp:82-83 [...]	Coverage: 0.04%

0x25a3f0 VXORPD	%XMM0,%XMM0,%XMM0

0x25a3f4 MOV	(%RBX),%RAX

0x25a3f7 VMOVSD	%XMM0,(%RAX,%R14,8)

0x25a3fd INC	%R14

0x25a400 CMP	%R14,0x260(%R12)

0x25a408 JBE	25a578

0x25a40e MOV	(%R13),%RAX

0x25a412 MOV	%R13,%RDI

0x25a415 MOV	%R12,%RSI

0x25a418 MOV	%R14D,%EDX

0x25a41b MOV	%R15,%RCX

0x25a41e VZEROUPPER

0x25a421 CALLQ	0x10(%RAX)

0x25a424 MOV	0x8(%R15),%RDX

0x25a428 TEST	%EDX,%EDX

0x25a42a JLE	25a3f0

0x25a42c MOV	-0x30(%RBP),%RCX

0x25a430 MOV	0x18(%R15),%RAX

0x25a434 MOV	%EDX,%EDX

0x25a436 MOV	0x18(%RCX),%RCX

0x25a43a CMP	$0x4,%EDX

0x25a43d JAE	25a450

0x25a43f VXORPD	%XMM0,%XMM0,%XMM0

0x25a443 XOR	%ESI,%ESI

0x25a445 JMP	25a560

0x25a450 CMP	$0x20,%EDX

0x25a453 JAE	25a460

0x25a455 VXORPD	%XMM0,%XMM0,%XMM0

0x25a459 XOR	%ESI,%ESI

0x25a45b JMP	25a508

0x25a460 MOV	%EDX,%EDI

0x25a462 MOV	%EDX,%ESI

0x25a464 AND	$0x1f,%EDI

0x25a467 AND	$-0x20,%ESI

0x25a46a VXORPD	%XMM0,%XMM0,%XMM0

0x25a46e VXORPD	%XMM1,%XMM1,%XMM1

0x25a472 VXORPD	%XMM2,%XMM2,%XMM2

0x25a476 VXORPD	%XMM3,%XMM3,%XMM3

0x25a47a XOR	%R8D,%R8D

0x25a47d NOPL	(%RAX)

  (833) 0x25a480 VMOVUPD	(%RCX,%R8,8),%ZMM4

  (833) 0x25a487 VMOVUPD	0x40(%RCX,%R8,8),%ZMM5

  (833) 0x25a48f VMOVUPD	0x80(%RCX,%R8,8),%ZMM6

  (833) 0x25a497 VMOVUPD	0xc0(%RCX,%R8,8),%ZMM7

  (833) 0x25a49f VFMADD231PD	(%RAX,%R8,8),%ZMM4,%ZMM0

  (833) 0x25a4a6 VFMADD231PD	0x40(%RAX,%R8,8),%ZMM5,%ZMM1

  (833) 0x25a4ae VFMADD231PD	0x80(%RAX,%R8,8),%ZMM6,%ZMM2

  (833) 0x25a4b6 VFMADD231PD	0xc0(%RAX,%R8,8),%ZMM7,%ZMM3

  (833) 0x25a4be ADD	$0x20,%R8

  (833) 0x25a4c2 CMP	%R8,%RSI

  (833) 0x25a4c5 JNE	25a480

0x25a4c7 VADDPD	%ZMM0,%ZMM1,%ZMM0

0x25a4cd VADDPD	%ZMM2,%ZMM3,%ZMM2

0x25a4d3 VADDPD	%ZMM0,%ZMM2,%ZMM0

0x25a4d9 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

0x25a4e0 VADDPD	%ZMM1,%ZMM0,%ZMM0

0x25a4e6 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x25a4ec VADDPD	%XMM1,%XMM0,%XMM0

0x25a4f0 VPERMILPD	$0x1,%XMM0,%XMM1

0x25a4f6 VADDSD	%XMM1,%XMM0,%XMM0

0x25a4fa TEST	%RDI,%RDI

0x25a4fd JE	25a3f4

0x25a503 CMP	$0x4,%EDI

0x25a506 JB	25a560

0x25a508 MOV	%EDX,%EDI

0x25a50a MOV	%RSI,%R8

0x25a50d MOV	%EDX,%ESI

0x25a50f AND	$0x3,%EDI

0x25a512 AND	$-0x4,%ESI

0x25a515 VMOVQ	%XMM0,%XMM0

0x25a519 NOPL	(%RAX)

  (835) 0x25a520 VMOVUPD	(%RCX,%R8,8),%YMM1

  (835) 0x25a526 VFMADD231PD	(%RAX,%R8,8),%YMM1,%YMM0

  (835) 0x25a52c ADD	$0x4,%R8

  (835) 0x25a530 CMP	%R8,%RSI

  (835) 0x25a533 JNE	25a520

0x25a535 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x25a53b VADDPD	%XMM1,%XMM0,%XMM0

0x25a53f VPERMILPD	$0x1,%XMM0,%XMM1

0x25a545 VADDSD	%XMM1,%XMM0,%XMM0

0x25a549 TEST	%RDI,%RDI

0x25a54c JE	25a3f4

0x25a552 NOPW	%CS:(%RAX,%RAX,1)

  (834) 0x25a560 VMOVSD	(%RCX,%RSI,8),%XMM1

  (834) 0x25a565 VFMADD231SD	(%RAX,%RSI,8),%XMM1,%XMM0

  (834) 0x25a56b INC	%RSI

  (834) 0x25a56e CMP	%RSI,%RDX

  (834) 0x25a571 JNE	25a560

0x25a573 JMP	25a3f4

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 82 - 83

--------------------------------------------------------------------------------

82:   for (int i = 0; i < n; i++)

83:     res += a[i] * b[i];

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 178 - 178

--------------------------------------------------------------------------------

178:   inline size_t size() const { return nLocal; }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1046

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h: 83 - 86

--------------------------------------------------------------------------------

83:     for (int iat = 0; iat < VP.getTotalNum(); ++iat)

84:     {

85:       evaluate(VP, iat, psi);

86:       ratios[iat] = simd::dot(psi.data(), psiinv.data(), psi.size());

Path /

Metric	Value
CQA speedup if no scalar integer	1.89
CQA speedup if FP arith vectorized	1.05
CQA speedup if fully vectorized	1.32
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.89
Bottlenecks	micro-operation queue,
Function	_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E
Source	inner_product.hpp:82-82,OhmmsVector.h:178-178,stl_vector.h:1046-1046,SPOSet.h:83-86
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.33
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	10.79
CQA cycles if fully vectorized	8.56
Front-end cycles	11.33
DIV/SQRT cycles	5.50
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	5.50
P4 cycles	3.33
P5 cycles	3.33
P6 cycles	3.33
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	68.00
Nb uops	68.00
Nb loads	8.00
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	3.35
Nb FLOP add-sub	38.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.35
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	46.34
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	75.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	41.94
Vector-efficiency ratio all	24.24
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	59.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.93

Metric	Value
CQA speedup if no scalar integer	1.89
CQA speedup if FP arith vectorized	1.05
CQA speedup if fully vectorized	1.32
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.89
Bottlenecks	micro-operation queue,
Function	_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E
Source	inner_product.hpp:82-82,OhmmsVector.h:178-178,stl_vector.h:1046-1046,SPOSet.h:83-86
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.33
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	10.79
CQA cycles if fully vectorized	8.56
Front-end cycles	11.33
DIV/SQRT cycles	5.50
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	5.50
P4 cycles	3.33
P5 cycles	3.33
P6 cycles	3.33
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	68.00
Nb uops	68.00
Nb loads	8.00
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	3.35
Nb FLOP add-sub	38.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.35
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	46.34
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	75.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	41.94
Vector-efficiency ratio all	24.24
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	59.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.93

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E
Source file and lines	inner_product.hpp:82-83
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:83-86

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.33 to 6.00 cycles (1.89x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 24% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 11.33 to 8.56 cycles (1.32x speedup).

Details

46% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
75% of SSE/AVX addition or subtraction instructions are used in vector version.
41% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 4 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 38 FP arithmetical operations:

38: addition or subtraction

The binary loop is loading 64 bytes (8 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.53 FP operations per loaded or stored byte.

General properties

nb instructions	68
nb uops	68
loop length	275
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	4
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.33 cycles
front end	11.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.50	4.00	4.00	4.00	5.50	3.33	3.33	3.33	3.00	3.00	4.00	4.00	0.50	0.50
cycles	5.50	4.00	4.00	4.00	5.50	3.33	3.33	3.33	3.00	3.00	6.00	6.00	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.33
Dispatch	6.00
Overall L1	11.33

Vectorization ratios

INT

all	5%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	5%

all	85%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	46%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	41%

Vector efficiency ratios

INT

all	9%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	38%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

INT+FP

all	24%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.33 cycles. At this rate:

5% of peak load performance is reached (5.65 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.71 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.33 to 6.00 cycles (1.89x speedup).

ASM code

In the binary file, the address of the loop is: 25a40e

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV (%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM0,(%RAX,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
INC %R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R14,0x260(%R12)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JBE 25a578 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x1c8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%R13),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
CALLQ 0x10(%RAX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	0	0	0	0	0	0	2.20
MOV 0x8(%R15),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
TEST %EDX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 25a3f0 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x40>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV -0x30(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x18(%R15),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x18(%RCX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP $0x4,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 25a450 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0xa0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 25a560 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
CMP $0x20,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 25a460 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0xb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 25a508 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x158>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %EDX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $0x1f,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
AND $-0x20,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM2,%ZMM3,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM0,%ZMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VADDPD %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VPERMILPD $0x1,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
TEST %RDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 25a3f4 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x44>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x4,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JB 25a560 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %EDX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $0x3,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
AND $-0x4,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VPERMILPD $0x1,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
TEST %RDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 25a3f4 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x44>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
JMP 25a3f4 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x44>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E
Source file and lines	inner_product.hpp:82-83
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:83-86

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.33 to 6.00 cycles (1.89x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

46% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
75% of SSE/AVX addition or subtraction instructions are used in vector version.
41% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 38 FP arithmetical operations:

38: addition or subtraction

The binary loop is loading 64 bytes (8 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.53 FP operations per loaded or stored byte.

General properties

nb instructions	68
nb uops	68
loop length	275
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	4
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.33 cycles
front end	11.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.50	4.00	4.00	4.00	5.50	3.33	3.33	3.33	3.00	3.00	4.00	4.00	0.50	0.50
cycles	5.50	4.00	4.00	4.00	5.50	3.33	3.33	3.33	3.00	3.00	6.00	6.00	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.33
Dispatch	6.00
Overall L1	11.33

Vectorization ratios

INT

all	5%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	5%

all	85%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	46%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	41%

Vector efficiency ratios

INT

all	9%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	38%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

INT+FP

all	24%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.33 cycles. At this rate:

5% of peak load performance is reached (5.65 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.71 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 25a40e

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV (%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM0,(%RAX,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
INC %R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R14,0x260(%R12)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JBE 25a578 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x1c8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%R13),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
CALLQ 0x10(%RAX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	0	0	0	0	0	0	2.20
MOV 0x8(%R15),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
TEST %EDX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 25a3f0 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x40>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV -0x30(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x18(%R15),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x18(%RCX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP $0x4,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 25a450 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0xa0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 25a560 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
CMP $0x20,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 25a460 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0xb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 25a508 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x158>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %EDX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $0x1f,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
AND $-0x20,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM2,%ZMM3,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM0,%ZMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VADDPD %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VPERMILPD $0x1,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
TEST %RDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 25a3f4 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x44>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x4,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JB 25a560 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %EDX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $0x3,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
AND $-0x4,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VPERMILPD $0x1,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
TEST %RDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 25a3f4 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x44>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
JMP 25a3f4 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x44>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code