OV - exec - Loop 64

	Loop Id: 64	Module: exec	Source: NonLocalPP.hpp:131-132 [...]	Coverage: 0.01%

0x22c420 MOV	(%R14),%RDX    [2]

0x22c423 MOV	(%RBX),%RDI    [8]

0x22c426 MOV	-0x10(%RBX),%R9    [8]

0x22c42a MOV	-0x80(%RBP),%R10    [12]

0x22c42e INC	%RCX

0x22c431 VMOVDDUP	(%RDX,%R12,8),%XMM1    [9]

0x22c437 SAL	$0x20,%R9

0x22c43b LEA	(%RDI,%R12,8),%R8

0x22c43f VMOVSD	(%RDI,%R12,8),%XMM2    [1]

0x22c445 VMOVSD	(%R10,%RAX,1),%XMM0    [7]

0x22c44b LEA	(%R13,%R13,2),%RDI

0x22c450 MOV	%R9,%RDX

0x22c453 SAR	$0x1d,%RDX

0x22c457 SAR	$0x1c,%R9

0x22c45b VMOVHPD	(%RDX,%R8,1),%XMM2,%XMM2    [11]

0x22c461 MOV	0x40(%RSI),%RDX    [5]

0x22c465 VFMADD213SD	(%R9,%R8,1),%XMM1,%XMM0    [10]

0x22c46b VFMADD231PD	-0x10(%R10,%RAX,1),%XMM1,%XMM2    [7]

0x22c472 VADDSD	0x10(%RDX,%RDI,8),%XMM0,%XMM0    [6]

0x22c478 VADDPD	(%RDX,%RDI,8),%XMM2,%XMM1    [6]

0x22c47d MOV	-0x40(%RBP),%RDX    [12]

0x22c481 VMOVUPD	%XMM1,-0x10(%RDX,%RAX,1)    [3]

0x22c487 VMOVSD	%XMM0,(%RDX,%RAX,1)    [3]

0x22c48c ADD	$0x18,%RAX

0x22c490 MOV	0x13f0(%R15),%RDX    [4]

0x22c497 SUB	0x13e8(%R15),%RDX    [4]

0x22c49e SHR	$0x3,%RDX

0x22c4a2 IMUL	$-0x55555555,%EDX,%EDX

0x22c4a8 MOVSXD	%EDX,%RDX

0x22c4ab CMP	%RDX,%RCX

0x22c4ae JL	22c420

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 231

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 144 - 145

--------------------------------------------------------------------------------

144:     for (int i = 0; i < D; ++i)

145:       X[i] = base[i * offset];

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 229

--------------------------------------------------------------------------------

223:     return X[i];

[...]

229:     return X[i];

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 919 - 1046

--------------------------------------------------------------------------------

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1046: 	return *(this->_M_impl._M_start + __n);

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 43 - 63

--------------------------------------------------------------------------------

43:     return (a + b);

[...]

63:     return (a * b);

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp: 131 - 132

--------------------------------------------------------------------------------

131:           for (int k = 0; k < size(); k++)

132:             virtualPos[k] = dist[iat] * rOnSphere[k] + displ[iat] + els.R[jel];

Path /

Metric	Value
CQA speedup if no scalar integer	1.20
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	3.69
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P5, P6, P7,
Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source	VectorSoAContainer.h:231-231,TinyVector.h:144-145,OhmmsVector.h:223-223,OhmmsVector.h:229-229,stl_vector.h:919-919,stl_vector.h:1046-1046,OperatorTags.h:43-43,OperatorTags.h:63-63,NonLocalPP.hpp:131-132
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	1.63
Front-end cycles	5.00
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	0.50
P4 cycles	6.00
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	1.00
P8 cycles	1.33
P9 cycles	1.33
P10 cycles	1.33
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	30.00
Nb loads	16.00
Nb stores	2.00
Nb stack references	2.00
FLOP/cycle	1.50
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	24.00
Stride 0	5.00
Stride 1	0.00
Stride n	2.00
Stride unknown	4.00
Stride indirect	1.00
Vectorization ratio all	30.00
Vectorization ratio load	25.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	50.00
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	16.25
Vector-efficiency ratio load	15.63
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	18.75
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.20
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	3.69
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P5, P6, P7,
Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source	VectorSoAContainer.h:231-231,TinyVector.h:144-145,OhmmsVector.h:223-223,OhmmsVector.h:229-229,stl_vector.h:919-919,stl_vector.h:1046-1046,OperatorTags.h:43-43,OperatorTags.h:63-63,NonLocalPP.hpp:131-132
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	1.63
Front-end cycles	5.00
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	0.50
P4 cycles	6.00
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	1.00
P8 cycles	1.33
P9 cycles	1.33
P10 cycles	1.33
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	30.00
Nb loads	16.00
Nb stores	2.00
Nb stack references	2.00
FLOP/cycle	1.50
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	24.00
Stride 0	5.00
Stride 1	0.00
Stride n	2.00
Stride unknown	4.00
Stride indirect	1.00
Vectorization ratio all	30.00
Vectorization ratio load	25.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	50.00
Vectorization ratio fma	50.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	16.25
Vector-efficiency ratio load	15.63
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	18.75
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source file and lines	NonLocalPP.hpp:131-132
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:144-145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:131-132

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 5.00 cycles (1.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 6.00 to 1.62 cycles (3.69x speedup).

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

25% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 5.00 cycles (1.20x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 3 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)
Constant non-unit stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 9 FP arithmetical operations:

6: addition or subtraction (3 inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 144 bytes (18 double precision FP elements). The binary loop is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	31
nb uops	30
loop length	148
used x86 registers	14
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.00	3.00	2.75	2.75	0.50	6.00	6.00	6.00	1.00	1.33	1.33	1.33	1.00	1.00
cycles	3.00	3.00	2.75	2.75	0.50	6.00	6.00	6.00	1.00	1.33	1.33	1.33	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.00
Dispatch	6.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

all	30%
load	25%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	16%
load	15%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 22c420

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV (%R14),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RBX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x10(%RBX),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x80(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INC %RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVDDUP (%RDX,%R12,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
SAL $0x20,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA (%RDI,%R12,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RDI,%R12,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%R10,%RAX,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R13,%R13,2),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R9,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAR $0x1d,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SAR $0x1c,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
VMOVHPD (%RDX,%R8,1),%XMM2,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV 0x40(%RSI),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VFMADD213SD (%R9,%R8,1),%XMM1,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD -0x10(%R10,%RAX,1),%XMM1,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VADDSD 0x10(%RDX,%RDI,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VADDPD (%RDX,%RDI,8),%XMM2,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOV -0x40(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVUPD %XMM1,-0x10(%RDX,%RAX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVSD %XMM0,(%RDX,%RAX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x18,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x13f0(%R15),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SUB 0x13e8(%R15),%RDX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
SHR $0x3,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
IMUL $-0x55555555,%EDX,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JL 22c420 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x2f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source file and lines	NonLocalPP.hpp:131-132
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:144-145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:131-132

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 5.00 cycles (1.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

25% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX fused multiply-add instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 5.00 cycles (1.20x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 3 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)
Constant non-unit stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 9 FP arithmetical operations:

6: addition or subtraction (3 inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 144 bytes (18 double precision FP elements). The binary loop is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	31
nb uops	30
loop length	148
used x86 registers	14
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.00	3.00	2.75	2.75	0.50	6.00	6.00	6.00	1.00	1.33	1.33	1.33	1.00	1.00
cycles	3.00	3.00	2.75	2.75	0.50	6.00	6.00	6.00	1.00	1.33	1.33	1.33	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.00
Dispatch	6.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

all	30%
load	25%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	16%
load	15%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	18%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 22c420

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV (%R14),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RBX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x10(%RBX),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x80(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INC %RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVDDUP (%RDX,%R12,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
SAL $0x20,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA (%RDI,%R12,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RDI,%R12,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%R10,%RAX,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (%R13,%R13,2),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R9,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAR $0x1d,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SAR $0x1c,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
VMOVHPD (%RDX,%R8,1),%XMM2,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
MOV 0x40(%RSI),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VFMADD213SD (%R9,%R8,1),%XMM1,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD -0x10(%R10,%RAX,1),%XMM1,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VADDSD 0x10(%RDX,%RDI,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VADDPD (%RDX,%RDI,8),%XMM2,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOV -0x40(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVUPD %XMM1,-0x10(%RDX,%RAX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVSD %XMM0,(%RDX,%RAX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x18,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x13f0(%R15),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SUB 0x13e8(%R15),%RDX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
SHR $0x3,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
IMUL $-0x55555555,%EDX,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JL 22c420 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x2f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code