OV - exec - Loop 63

	Loop Id: 63	Module: exec	Source: NonLocalPP.hpp:126-135 [...]	Coverage: 0.08%

0x22c3d0 MOV	0x1418(%R15),%RCX

0x22c3d7 MOV	-0x68(%RBP),%RSI

0x22c3db INC	%R12

0x22c3de CMP	%R12,0x260(%RCX)

0x22c3e5 JBE	22c380

0x22c3e7 MOV	(%R14),%RAX

0x22c3ea VMOVSD	(%RAX,%R12,8),%XMM0

0x22c3f0 VUCOMISD	(%R15),%XMM0

0x22c3f5 JAE	22c3db

0x22c3f7 MOV	0x13f0(%R15),%RAX

0x22c3fe SUB	0x13e8(%R15),%RAX

0x22c405 SHR	$0x3,%RAX

0x22c409 IMUL	$-0x55555555,%EAX,%EAX

0x22c40f TEST	%EAX,%EAX

0x22c411 JLE	22c4bb

0x22c417 MOV	$0x10,%EAX

0x22c41c XOR	%ECX,%ECX

0x22c41e XCHG	%AX,%AX

  (64) 0x22c420 MOV	(%R14),%RDX

  (64) 0x22c423 MOV	(%RBX),%RDI

  (64) 0x22c426 MOV	-0x10(%RBX),%R9

  (64) 0x22c42a MOV	-0x80(%RBP),%R10

  (64) 0x22c42e INC	%RCX

  (64) 0x22c431 VMOVDDUP	(%RDX,%R12,8),%XMM1

  (64) 0x22c437 SAL	$0x20,%R9

  (64) 0x22c43b LEA	(%RDI,%R12,8),%R8

  (64) 0x22c43f VMOVSD	(%RDI,%R12,8),%XMM2

  (64) 0x22c445 VMOVSD	(%R10,%RAX,1),%XMM0

  (64) 0x22c44b LEA	(%R13,%R13,2),%RDI

  (64) 0x22c450 MOV	%R9,%RDX

  (64) 0x22c453 SAR	$0x1d,%RDX

  (64) 0x22c457 SAR	$0x1c,%R9

  (64) 0x22c45b VMOVHPD	(%RDX,%R8,1),%XMM2,%XMM2

  (64) 0x22c461 MOV	0x40(%RSI),%RDX

  (64) 0x22c465 VFMADD213SD	(%R9,%R8,1),%XMM1,%XMM0

  (64) 0x22c46b VFMADD231PD	-0x10(%R10,%RAX,1),%XMM1,%XMM2

  (64) 0x22c472 VADDSD	0x10(%RDX,%RDI,8),%XMM0,%XMM0

  (64) 0x22c478 VADDPD	(%RDX,%RDI,8),%XMM2,%XMM1

  (64) 0x22c47d MOV	-0x40(%RBP),%RDX

  (64) 0x22c481 VMOVUPD	%XMM1,-0x10(%RDX,%RAX,1)

  (64) 0x22c487 VMOVSD	%XMM0,(%RDX,%RAX,1)

  (64) 0x22c48c ADD	$0x18,%RAX

  (64) 0x22c490 MOV	0x13f0(%R15),%RDX

  (64) 0x22c497 SUB	0x13e8(%R15),%RDX

  (64) 0x22c49e SHR	$0x3,%RDX

  (64) 0x22c4a2 IMUL	$-0x55555555,%EDX,%EDX

  (64) 0x22c4a8 MOVSXD	%EDX,%RDX

  (64) 0x22c4ab CMP	%RDX,%RCX

  (64) 0x22c4ae JL	22c420

0x22c4b4 MOV	0x1418(%R15),%RCX

0x22c4bb MOV	0x18(%RCX),%RAX

0x22c4bf MOV	0x1400(%R15),%RCX

0x22c4c6 MOVSXD	(%RAX,%R12,4),%RAX

0x22c4ca MOV	(%RCX,%RAX,8),%RDI

0x22c4ce LEA	-0x40(%RBP),%RCX

0x22c4d2 MOV	$0x1,%R8D

0x22c4d8 MOV	%RDI,-0xa8(%RBP)

0x22c4df MOV	%R13D,%EDX

0x22c4e2 MOV	%R12D,%R9D

0x22c4e5 CALL	29f7e0 <_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi>

0x22c4ea MOV	-0x70(%RBP),%RDI

0x22c4ee MOV	-0xa8(%RBP),%RSI

0x22c4f5 LEA	-0x60(%RBP),%RDX

0x22c4f9 CALL	22ff30 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE>

0x22c4fe JMP	22c3d0

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 231

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 144 - 145

--------------------------------------------------------------------------------

144:     for (int i = 0; i < D; ++i)

145:       X[i] = base[i * offset];

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 229

--------------------------------------------------------------------------------

223:     return X[i];

[...]

229:     return X[i];

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 919 - 1046

--------------------------------------------------------------------------------

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1046: 	return *(this->_M_impl._M_start + __n);

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 43 - 63

--------------------------------------------------------------------------------

43:     return (a + b);

[...]

63:     return (a * b);

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h: 173 - 173

--------------------------------------------------------------------------------

173:       pointer    _M_ptr() const { return std::get<0>(_M_t); }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp: 126 - 135

--------------------------------------------------------------------------------

126:       for (int iat = 0; iat < ions_ref.getTotalNum(); ++iat)

127:       {

128:         //due to < Rmax condition, the actually iteration iat is [0,2] in a real simulation

129:         if (dist[iat] < Rmax)

130:         {

131:           for (int k = 0; k < size(); k++)

132:             virtualPos[k] = dist[iat] * rOnSphere[k] + displ[iat] + els.R[jel];

133:           auto& VP = *VPs[ions_ref.GroupID[iat]];

134:           VP.makeMoves(els, jel, virtualPos, true, iat);

135:           wf.evaluateRatios(VP, ratios);

Path /

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.46
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks
Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source	OhmmsVector.h:229-229,stl_vector.h:919-919,stl_vector.h:1046-1046,unique_ptr.h:173-173,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.33
CQA cycles if no scalar integer	1.44
CQA cycles if FP arith vectorized	4.33
CQA cycles if fully vectorized	0.97
Front-end cycles	4.28
DIV/SQRT cycles	2.58
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.42
P3 cycles	2.33
P4 cycles	4.33
P5 cycles	4.33
P6 cycles	4.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.67
Nb uops	25.67
Nb loads	11.00
Nb stores	0.67
Nb stack references	3.33
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.71
Bytes prefetched	0.00
Bytes loaded	85.33
Bytes stored	5.33
Stride 0	3.00
Stride 1	1.33
Stride n	3.00
Stride unknown	1.33
Stride indirect	0.33
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.36
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.00

Metric	Value
CQA speedup if no scalar integer	1.14
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	micro-operation queue, P5, P6, P7,
Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source	OhmmsVector.h:229-229,stl_vector.h:919-919,stl_vector.h:1046-1046,unique_ptr.h:173-173,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.33
CQA cycles if no scalar integer	1.17
CQA cycles if FP arith vectorized	1.33
CQA cycles if fully vectorized	0.33
Front-end cycles	1.33
DIV/SQRT cycles	1.00
P0 cycles	0.75
P1 cycles	0.75
P2 cycles	0.50
P3 cycles	1.00
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	7.00
Nb uops	8.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	0.00
Stride n	1.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	3.60
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.71
Bottlenecks	micro-operation queue,
Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source	OhmmsVector.h:229-229,stl_vector.h:919-919,stl_vector.h:1046-1046,unique_ptr.h:173-173,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	1.67
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	1.33
Front-end cycles	6.00
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	3.50
P3 cycles	3.00
P4 cycles	6.00
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	34.00
Nb uops	36.00
Nb loads	15.00
Nb stores	1.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.67
Bytes prefetched	0.00
Bytes loaded	116.00
Bytes stored	8.00
Stride 0	4.00
Stride 1	4.00
Stride n	5.00
Stride unknown	2.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.80
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.75

Metric	Value
CQA speedup if no scalar integer	3.78
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.53
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P5, P6, P7,
Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source	OhmmsVector.h:229-229,stl_vector.h:919-919,stl_vector.h:1046-1046,unique_ptr.h:173-173,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.67
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	5.67
CQA cycles if fully vectorized	1.25
Front-end cycles	5.50
DIV/SQRT cycles	3.25
P0 cycles	3.25
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.00
P4 cycles	5.67
P5 cycles	5.67
P6 cycles	5.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	33.00
Nb loads	14.00
Nb stores	1.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.47
Bytes prefetched	0.00
Bytes loaded	108.00
Bytes stored	8.00
Stride 0	3.00
Stride 1	0.00
Stride n	3.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.80
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source file and lines	NonLocalPP.hpp:126-135
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:144-145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h:173
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.33 to 0.97 cycles (4.46x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 85 bytes (10 double precision FP elements). The binary loop is storing 5 bytes (0 double precision FP elements).

General properties

nb instructions	23.67
nb uops	25.67
loop length	110
used x86 registers	9.67
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	3.33

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	4.28 cycles
front end	4.28 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.58	2.50	2.50	2.42	2.33	4.33	4.33	4.33	0.00	0.00	0.50	0.50	0.50	0.50
cycles	2.58	2.50	2.50	2.42	2.33	4.33	4.33	4.33	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.28
Dispatch	4.33
Data deps.	1.00
Overall L1	4.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.33 cycles. At this rate:

21% of peak load performance is reached (20.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.92 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source file and lines	NonLocalPP.hpp:126-135
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:144-145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h:173
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.33 to 1.17 cycles (1.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 1.33 to 0.33 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.33 to 1.00 cycles (1.33x speedup).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes (4 double precision FP elements).

General properties

nb instructions	7
nb uops	8
loop length	28
used x86 registers	5
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.33 cycles
front end	1.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	0.75	0.75	0.50	1.00	1.33	1.33	1.33	0.00	0.00	0.50	0.50	0.50	0.50
cycles	1.00	0.75	0.75	0.50	1.00	1.33	1.33	1.33	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.33
Dispatch	1.33
Data deps.	1.00
Overall L1	1.33

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.33 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.33 to 1.00 cycles (1.33x speedup).

ASM code

In the binary file, the address of the loop is: 22c3e7

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
INC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R12,0x260(%RCX)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
JBE 22c380 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x250>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV (%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%RAX,%R12,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VUCOMISD (%R15),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0.50	0.50	6	1
JAE 22c3db <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x2ab>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source file and lines	NonLocalPP.hpp:126-135
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:144-145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h:173
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 1.67 cycles (3.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 1.33 cycles (4.50x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE: 1 occurrences
_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Constant non-unit stride: 5 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 116 bytes (14 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

General properties

nb instructions	34
nb uops	36
loop length	159
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.50	3.50	3.50	3.50	3.00	6.00	6.00	6.00	0.00	0.00	0.50	0.50	0.50	0.50
cycles	3.50	3.50	3.50	3.50	3.00	6.00	6.00	6.00	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.00
Dispatch	6.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

20% of peak load performance is reached (19.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 22c3e7

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV 0x1418(%R15),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV -0x68(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
INC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R12,0x260(%RCX)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
JBE 22c380 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x250>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV (%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%RAX,%R12,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VUCOMISD (%R15),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0.50	0.50	6	1
JAE 22c3db <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x2ab>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV 0x13f0(%R15),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
SUB 0x13e8(%R15),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
SHR $0x3,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
IMUL $-0x55555555,%EAX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JLE 22c4bb <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x38b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV $0x10,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0x1418(%R15),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x18(%RCX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x1400(%R15),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOVSXD (%RAX,%R12,4),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
MOV (%RCX,%RAX,8),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
LEA -0x40(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV $0x1,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RDI,-0xa8(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV %R13D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 29f7e0 <_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV -0x70(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV -0xa8(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
LEA -0x60(%RBP),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CALL 22ff30 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
JMP 22c3d0 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x2a0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1

Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source file and lines	NonLocalPP.hpp:126-135
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:144-145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h:173
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.67 to 1.50 cycles (3.78x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

CALL instructions

Detected function call instructions.

Details

_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE: 1 occurrences
_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Constant non-unit stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 108 bytes (13 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

General properties

nb instructions	30
nb uops	33
loop length	143
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.25	3.25	3.25	3.25	3.00	5.67	5.67	5.67	0.00	0.00	0.50	0.50	0.50	0.50
cycles	3.25	3.25	3.25	3.25	3.00	5.67	5.67	5.67	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.50
Dispatch	5.67
Data deps.	1.00
Overall L1	5.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.67 cycles. At this rate:

19% of peak load performance is reached (19.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.41 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 22c3e7

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV 0x1418(%R15),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV -0x68(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
INC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R12,0x260(%RCX)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
JBE 22c380 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x250>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV (%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%RAX,%R12,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VUCOMISD (%R15),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0.50	0.50	6	1
JAE 22c3db <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x2ab>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV 0x13f0(%R15),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
SUB 0x13e8(%R15),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
SHR $0x3,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
IMUL $-0x55555555,%EAX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JLE 22c4bb <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x38b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV 0x18(%RCX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x1400(%R15),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOVSXD (%RAX,%R12,4),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
MOV (%RCX,%RAX,8),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
LEA -0x40(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV $0x1,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RDI,-0xa8(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV %R13D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 29f7e0 <_ZN11qmcplusplus18VirtualParticleSet9makeMovesERKNS_11ParticleSetEiRKSt6vectorINS_10TinyVectorIdLj3EEESaIS6_EEbi>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV -0x70(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV -0xa8(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
LEA -0x60(%RBP),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CALL 22ff30 <_ZN11qmcplusplus12WaveFunction14evaluateRatiosERNS_18VirtualParticleSetERSt6vectorIdSaIdEE>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
JMP 22c3d0 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x2a0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1

Report Configuration

Vectorization

Details

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end