OV - exec - Loop 32

	Loop Id: 32	Module: exec	Source: miniqmc.cpp:429-458 [...]	Coverage: 0.01%

0x22acc0 INCL	0x38(%RSP)    [9]

0x22acc4 MOV	0x50(%RSP),%RAX    [9]

0x22acc9 INC	%R15

0x22accc ADD	$0x18,%R12

0x22acd0 MOVSXD	(%RAX),%RAX    [5]

0x22acd3 CMP	%RAX,%R15

0x22acd6 JGE	22adf0

0x22acdc MOV	0x10(%RBP),%RAX    [7]

0x22ace0 MOV	(%RAX),%RAX    [8]

0x22ace3 MOV	0x28(%RAX),%RDI    [6]

0x22ace7 CALL	2a0a60 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x22acec MOV	0x40(%RSP),%RSI    [9]

0x22acf1 LEA	0x1e8(%RSP),%RDI

0x22acf9 MOV	%RBX,%RDX

0x22acfc MOV	%R15D,%ECX

0x22acff CALL	22f9c0 <_ZN11qmcplusplus12WaveFunction8evalGradERNS_11ParticleSetEi>

0x22ad04 MOV	0x10(%RBP),%RAX    [7]

0x22ad08 MOV	(%RAX),%RAX    [2]

0x22ad0b MOV	0x28(%RAX),%RDI    [1]

0x22ad0f CALL	2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x22ad14 MOV	$0x1,%ECX

0x22ad19 MOV	%RBX,%RDI

0x22ad1c MOV	%R15D,%ESI

0x22ad1f MOV	%R12,%RDX

0x22ad22 CALL	27cb30 <_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEEb>

0x22ad27 MOV	0x10(%RBP),%RAX    [7]

0x22ad2b MOV	(%RAX),%RAX    [2]

0x22ad2e MOV	0x30(%RAX),%RDI    [1]

0x22ad32 CALL	2a0a60 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x22ad37 VXORPD	%XMM0,%XMM0,%XMM0

0x22ad3b MOVQ	$0,0x170(%RSP)    [9]

0x22ad47 VMOVAPD	%XMM0,0x160(%RSP)    [9]

0x22ad50 MOV	0x40(%RSP),%RDI    [9]

0x22ad55 LEA	0x160(%RSP),%RCX

0x22ad5d MOV	%RBX,%RSI

0x22ad60 MOV	%R15D,%EDX

0x22ad63 CALL	22faa0 <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE>

0x22ad68 MOV	0x10(%RBP),%RAX    [7]

0x22ad6c MOV	(%RAX),%RAX    [2]

0x22ad6f MOV	0x30(%RAX),%RDI    [1]

0x22ad73 CALL	2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x22ad78 MOV	0x60(%RSP),%RAX    [9]

0x22ad7d MOV	0x28(%RBP),%RCX    [7]

0x22ad81 VMOVSD	(%RAX,%R15,8),%XMM0    [3]

0x22ad87 VUCOMISD	(%RCX),%XMM0    [4]

0x22ad8b JAE	22add0

0x22ad8d MOV	0x10(%RBP),%RAX    [7]

0x22ad91 MOV	(%RAX),%RAX    [2]

0x22ad94 MOV	0x38(%RAX),%RDI    [1]

0x22ad98 CALL	2a0a60 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x22ad9d MOV	0x40(%RSP),%RDI    [9]

0x22ada2 MOV	%RBX,%RSI

0x22ada5 MOV	%R15D,%EDX

0x22ada8 CALL	22fc70 <_ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi>

0x22adad MOV	0x10(%RBP),%RAX    [7]

0x22adb1 MOV	(%RAX),%RAX    [2]

0x22adb4 MOV	0x38(%RAX),%RDI    [1]

0x22adb8 CALL	2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x22adbd MOV	%RBX,%RDI

0x22adc0 MOV	%R15D,%ESI

0x22adc3 CALL	27d370 <_ZN11qmcplusplus11ParticleSet10acceptMoveEi>

0x22adc8 JMP	22acc0

0x22add0 MOV	%RBX,%RDI

0x22add3 MOV	%R15D,%ESI

0x22add6 CALL	27d6c0 <_ZN11qmcplusplus11ParticleSet10rejectMoveEi>

0x22addb MOV	0x40(%RSP),%RDI    [9]

0x22ade0 MOV	%R15D,%ESI

0x22ade3 CALL	22fd90 <_ZN11qmcplusplus12WaveFunction7restoreEi>

0x22ade8 JMP	22acc4

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 62 - 62

--------------------------------------------------------------------------------

62:       X[d] = T(0);

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1046

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/refwrap.h: 338 - 338

--------------------------------------------------------------------------------

338:       { return *_M_data; }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp: 429 - 458

--------------------------------------------------------------------------------

429:         for (int iel = 0; iel < nels; ++iel)

430:         {

431:           // Compute gradient at the current position

432:           Timers[Timer_evalGrad].get().start();

433:           PosType grad_now = wavefunction.evalGrad(els, iel);

434:           Timers[Timer_evalGrad].get().stop();

435:

436:           // Construct trial move

437:           els.makeMove(iel, delta[iel]);

438:

439:           // Compute gradient at the trial position

440:           Timers[Timer_ratioGrad].get().start();

441:           PosType grad_new;

442:           wavefunction.ratioGrad(els, iel, grad_new);

443:           Timers[Timer_ratioGrad].get().stop();

444:

445:           // Accept/reject the trial move

446:           if (ur[iel] < accept) // MC

447:           {

448:             // Update position, and update temporary storage

449:             Timers[Timer_Update].get().start();

450:             wavefunction.acceptMove(els, iel);

451:             Timers[Timer_Update].get().stop();

452:             els.acceptMove(iel);

453:             my_accepted++;

454:           }

455:           else

456:           {

457:             els.rejectMove(iel);

458:             wavefunction.restore(iel);

Path /

Metric	Value
CQA speedup if no scalar integer	2.28
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.24
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks
Function	.omp_outlined..64
Source	TinyVector.h:62-62,stl_vector.h:1046-1046,refwrap.h:338-338,miniqmc.cpp:429-458
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.17
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	12.17
CQA cycles if fully vectorized	2.32
Front-end cycles	11.42
DIV/SQRT cycles	6.50
P0 cycles	2.63
P1 cycles	2.50
P2 cycles	2.38
P3 cycles	6.50
P4 cycles	12.17
P5 cycles	12.17
P6 cycles	12.17
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	68.50
Nb loads	24.50
Nb stores	2.50
Nb stack references	8.50
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.74
Bytes prefetched	0.00
Bytes loaded	190.00
Bytes stored	26.00
Stride 0	2.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	8.39
Vectorization ratio load	0.00
Vectorization ratio store	41.67
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	8.71
Vector-efficiency ratio all	12.12
Vector-efficiency ratio load	12.24
Vector-efficiency ratio store	14.06
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.41

Metric	Value
CQA speedup if no scalar integer	2.28
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P5, P6, P7,
Function	.omp_outlined..64
Source	TinyVector.h:62-62,stl_vector.h:1046-1046,refwrap.h:338-338,miniqmc.cpp:429-458
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.67
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	13.67
CQA cycles if fully vectorized	2.60
Front-end cycles	12.50
DIV/SQRT cycles	7.00
P0 cycles	2.75
P1 cycles	2.75
P2 cycles	2.50
P3 cycles	7.00
P4 cycles	13.67
P5 cycles	13.67
P6 cycles	13.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	62.00
Nb uops	75.00
Nb loads	28.00
Nb stores	3.00
Nb stack references	9.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.85
Bytes prefetched	0.00
Bytes loaded	216.00
Bytes stored	28.00
Stride 0	2.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	7.69
Vectorization ratio load	0.00
Vectorization ratio store	33.33
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	8.33
Vector-efficiency ratio all	12.02
Vector-efficiency ratio load	11.98
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.46

Metric	Value
CQA speedup if no scalar integer	2.29
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P5, P6, P7,
Function	.omp_outlined..64
Source	TinyVector.h:62-62,stl_vector.h:1046-1046,refwrap.h:338-338,miniqmc.cpp:429-458
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.67
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	2.04
Front-end cycles	10.33
DIV/SQRT cycles	6.00
P0 cycles	2.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	6.00
P4 cycles	10.67
P5 cycles	10.67
P6 cycles	10.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	62.00
Nb loads	21.00
Nb stores	2.00
Nb stack references	8.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.63
Bytes prefetched	0.00
Bytes loaded	164.00
Bytes stored	24.00
Stride 0	2.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	9.09
Vectorization ratio load	0.00
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	9.09
Vector-efficiency ratio all	12.22
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	15.63
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.36

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..64
Source file and lines	miniqmc.cpp:429-458
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/refwrap.h:338
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp:429-458

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.17 to 2.32 cycles (5.24x speedup).

Details

8% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
41% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
8% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_ZN11qmcplusplus11ParticleSet10acceptMoveEi: 1 occurrences
_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEEb: 1 occurrences
_ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi: 1 occurrences
_ZN11qmcplusplus12WaveFunction8evalGradERNS_11ParticleSetEi: 1 occurrences
_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE: 1 occurrences
_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv: 2.50 occurrences
_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv: 2.50 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences
VUCOMISD: 1 occurrences

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 190 bytes (23 double precision FP elements). The binary loop is storing 26 bytes (3 double precision FP elements).

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	57
nb uops	68.50
loop length	249.50
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	8.50

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	11.42 cycles
front end	11.42 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.50	2.63	2.50	2.38	6.50	12.17	12.17	12.17	0.00	0.00	0.50	0.50	1.00	1.00
cycles	6.50	2.63	2.50	2.38	6.50	12.17	12.17	12.17	0.00	0.00	0.50	0.50	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	11.42
Dispatch	12.17
Data deps.	1.00
Overall L1	12.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	8%
load	0%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Vector efficiency ratios

INT

all	10%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	18%
load	12%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	12%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.17 cycles. At this rate:

16% of peak load performance is reached (15.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.15 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	.omp_outlined..64
Source file and lines	miniqmc.cpp:429-458
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/refwrap.h:338
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp:429-458

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.67 to 6.00 cycles (2.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

7% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
33% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
8% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 13.67 to 12.50 cycles (1.09x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

CALL instructions

Detected function call instructions.

Details

_ZN11qmcplusplus11ParticleSet10acceptMoveEi: 1 occurrences
_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEEb: 1 occurrences
_ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi: 1 occurrences
_ZN11qmcplusplus12WaveFunction8evalGradERNS_11ParticleSetEi: 1 occurrences
_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE: 1 occurrences
_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv: 3 occurrences
_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv: 3 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences
VUCOMISD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 216 bytes (27 double precision FP elements). The binary loop is storing 28 bytes (3 double precision FP elements).

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	62
nb uops	75
loop length	269
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.00	2.75	2.75	2.50	7.00	13.67	13.67	13.67	0.00	0.00	0.50	0.50	1.00	1.00
cycles	7.00	2.75	2.75	2.50	7.00	13.67	13.67	13.67	0.00	0.00	0.50	0.50	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	12.50
Dispatch	13.67
Data deps.	1.00
Overall L1	13.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	7%
load	0%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Vector efficiency ratios

INT

all	10%
load	11%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	18%
load	12%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	11%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.67 cycles. At this rate:

16% of peak load performance is reached (15.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.05 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 22acdc

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
INCL 0x38(%RSP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MOV 0x50(%RSP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
INC %R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSXD (%RAX),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
CMP %RAX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JGE 22adf0 <.omp_outlined..64+0x970>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV 0x10(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV (%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x28(%RAX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CALL 2a0a60 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x40(%RSP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
LEA 0x1e8(%RSP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 22f9c0 <_ZN11qmcplusplus12WaveFunction8evalGradERNS_11ParticleSetEi>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x10(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV (%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x28(%RAX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CALL 2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV $0x1,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 27cb30 <_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEEb>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x10(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV (%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x30(%RAX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CALL 2a0a60 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVQ $0,0x170(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
VMOVAPD %XMM0,0x160(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOV 0x40(%RSP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
LEA 0x160(%RSP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 22faa0 <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x10(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV (%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x30(%RAX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CALL 2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x60(%RSP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x28(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%RAX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VUCOMISD (%RCX),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0.50	0.50	6	1
JAE 22add0 <.omp_outlined..64+0x950>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV 0x10(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV (%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x38(%RAX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CALL 2a0a60 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x40(%RSP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 22fc70 <_ZN11qmcplusplus12WaveFunction10acceptMoveERNS_11ParticleSetEi>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x10(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV (%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x38(%RAX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CALL 2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 27d370 <_ZN11qmcplusplus11ParticleSet10acceptMoveEi>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
JMP 22acc0 <.omp_outlined..64+0x840>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1

Function	.omp_outlined..64
Source file and lines	miniqmc.cpp:429-458
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/refwrap.h:338
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp:429-458

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.67 to 4.67 cycles (2.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

9% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
9% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

CALL instructions

Detected function call instructions.

Details

_ZN11qmcplusplus11ParticleSet10rejectMoveEi: 1 occurrences
_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEEb: 1 occurrences
_ZN11qmcplusplus12WaveFunction7restoreEi: 1 occurrences
_ZN11qmcplusplus12WaveFunction8evalGradERNS_11ParticleSetEi: 1 occurrences
_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE: 1 occurrences
_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv: 2 occurrences
_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv: 2 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 164 bytes (20 double precision FP elements). The binary loop is storing 24 bytes (3 double precision FP elements).

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	52
nb uops	62
loop length	230
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.33 cycles
front end	10.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.00	2.50	2.25	2.25	6.00	10.67	10.67	10.67	0.00	0.00	0.50	0.50	1.00	1.00
cycles	6.00	2.50	2.25	2.25	6.00	10.67	10.67	10.67	0.00	0.00	0.50	0.50	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	10.33
Dispatch	10.67
Data deps.	1.00
Overall L1	10.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	9%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Vector efficiency ratios

INT

all	10%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	18%
load	12%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	12%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles. At this rate:

16% of peak load performance is reached (15.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.25 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 22acdc

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV 0x50(%RSP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
INC %R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSXD (%RAX),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
CMP %RAX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JGE 22adf0 <.omp_outlined..64+0x970>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV 0x10(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV (%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x28(%RAX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CALL 2a0a60 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x40(%RSP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
LEA 0x1e8(%RSP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 22f9c0 <_ZN11qmcplusplus12WaveFunction8evalGradERNS_11ParticleSetEi>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x10(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV (%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x28(%RAX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CALL 2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV $0x1,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 27cb30 <_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEEb>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x10(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV (%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x30(%RAX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CALL 2a0a60 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVQ $0,0x170(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
VMOVAPD %XMM0,0x160(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOV 0x40(%RSP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
LEA 0x160(%RSP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 22faa0 <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x10(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV (%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x30(%RAX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CALL 2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x60(%RSP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x28(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD (%RAX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VUCOMISD (%RCX),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0.50	0.50	6	1
JAE 22add0 <.omp_outlined..64+0x950>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 27d6c0 <_ZN11qmcplusplus11ParticleSet10rejectMoveEi>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x40(%RSP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 22fd90 <_ZN11qmcplusplus12WaveFunction7restoreEi>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
JMP 22acc4 <.omp_outlined..64+0x844>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1

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CALL instructions

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Complex instructions

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Slow data structures access

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

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General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

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Vectorization

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Execution units bottlenecks

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CALL instructions

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Complex instructions

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Slow data structures access

Details

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code