OV - exec - Loop 2036

	Loop Id: 2036	Module: exec	Source: ParticleBConds3DSoa.h:280-298 [...]	Coverage: 4.48%

0x2e20d0 MOV	-0x30(%RBP),%RCX    [7]

0x2e20d4 VMOVUPD	(%RAX,%RDI,8),%ZMM26    [3]

0x2e20db VPBROADCASTQ	-0xddfad(%RIP),%ZMM31    [4]

0x2e20e5 VMOVUPD	(%RCX,%RDI,8),%ZMM24    [1]

0x2e20ec MOV	-0xb8(%RBP),%RCX    [7]

0x2e20f3 VSUBPD	%ZMM23,%ZMM26,%ZMM26

0x2e20f9 VMOVDQA64	%ZMM31,%ZMM29

0x2e20ff VMOVDQA64	%ZMM31,%ZMM30

0x2e2105 VMOVUPD	(%RCX,%RDI,8),%ZMM25    [6]

0x2e210c MOV	-0xb0(%RBP),%RCX    [7]

0x2e2113 VSUBPD	%ZMM21,%ZMM24,%ZMM24

0x2e2119 VMULPD	%ZMM24,%ZMM0,%ZMM27

0x2e211f VMULPD	%ZMM24,%ZMM3,%ZMM28

0x2e2125 VMULPD	%ZMM24,%ZMM6,%ZMM24

0x2e212b VSUBPD	%ZMM22,%ZMM25,%ZMM25

0x2e2131 VFMADD231PD	%ZMM25,%ZMM1,%ZMM27

0x2e2137 VFMADD231PD	%ZMM25,%ZMM4,%ZMM28

0x2e213d VFMADD231PD	%ZMM25,%ZMM7,%ZMM24

0x2e2143 VPBROADCASTQ	-0xddebd(%RIP),%ZMM25    [4]

0x2e214d VFMADD231PD	%ZMM26,%ZMM2,%ZMM27

0x2e2153 VFMADD231PD	%ZMM26,%ZMM5,%ZMM28

0x2e2159 VFMADD231PD	%ZMM26,%ZMM8,%ZMM24

0x2e215f VPTERNLOGQ	$-0x8,%ZMM25,%ZMM27,%ZMM29

0x2e2166 VPTERNLOGQ	$-0x8,%ZMM25,%ZMM28,%ZMM30

0x2e216d VPTERNLOGQ	$-0x8,%ZMM25,%ZMM24,%ZMM31

0x2e2174 VADDPD	%ZMM29,%ZMM27,%ZMM29

0x2e217a VADDPD	%ZMM31,%ZMM24,%ZMM25

0x2e2180 VRNDSCALEPD	$0xb,%ZMM29,%ZMM29

0x2e2187 VRNDSCALEPD	$0xb,%ZMM25,%ZMM25

0x2e218e VSUBPD	%ZMM29,%ZMM27,%ZMM27

0x2e2194 VADDPD	%ZMM30,%ZMM28,%ZMM29

0x2e219a VSUBPD	%ZMM25,%ZMM24,%ZMM24

0x2e21a0 VRNDSCALEPD	$0xb,%ZMM29,%ZMM29

0x2e21a7 VMULPD	%ZMM27,%ZMM12,%ZMM26

0x2e21ad VSUBPD	%ZMM29,%ZMM28,%ZMM28

0x2e21b3 VMULPD	%ZMM27,%ZMM9,%ZMM29

0x2e21b9 VMULPD	%ZMM27,%ZMM15,%ZMM27

0x2e21bf VFMADD231PD	%ZMM28,%ZMM10,%ZMM29

0x2e21c5 VFMADD231PD	%ZMM28,%ZMM13,%ZMM26

0x2e21cb VFMADD231PD	%ZMM28,%ZMM16,%ZMM27

0x2e21d1 VFMADD231PD	%ZMM11,%ZMM24,%ZMM29

0x2e21d7 VFMADD231PD	%ZMM24,%ZMM14,%ZMM26

0x2e21dd VFMADD231PD	%ZMM24,%ZMM17,%ZMM27

0x2e21e3 VMOVUPD	%ZMM29,(%R8,%RDI,8)    [8]

0x2e21ea VMOVUPD	%ZMM26,(%R9,%RDI,8)    [2]

0x2e21f1 VMOVUPD	%ZMM27,(%RCX,%RDI,8)    [5]

0x2e21f8 VMOVUPD	(%R8,%RDI,8),%ZMM24    [8]

0x2e21ff VMOVUPD	(%R9,%RDI,8),%ZMM26    [2]

0x2e2206 VMULPD	%ZMM24,%ZMM24,%ZMM24

0x2e220c VFMADD231PD	%ZMM27,%ZMM27,%ZMM24

0x2e2212 VFMADD231PD	%ZMM26,%ZMM26,%ZMM24

0x2e2218 VSQRTPD	%ZMM24,%ZMM24

0x2e221e VMOVUPD	%ZMM24,(%R14,%RDI,8)    [9]

0x2e2225 ADD	$0x8,%RDI

0x2e2229 CMP	%RDI,%R11

0x2e222c JNE	2e20d0

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h: 228 - 228

--------------------------------------------------------------------------------

228:           for (int iel = first; iel < last; iel++)

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 280 - 298

--------------------------------------------------------------------------------

280:     T displ_0 = px[iat] - x0;

281:     T displ_1 = py[iat] - y0;

282:     T displ_2 = pz[iat] - z0;

283:

284:     T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

285:     T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

286:     T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

287:

288:     //put them in the box

289:     ar_0 -= round(ar_0);

290:     ar_1 -= round(ar_1);

291:     ar_2 -= round(ar_2);

292:

293:     //unit2cart

294:     dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

295:     dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

296:     dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

297:

298:     temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P8, P9,
Function	_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE
Source	SoaDistanceTableABOMPTarget.h:228-228,ParticleBConds3DSoa.h:280-298
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	22.00
CQA cycles if no scalar integer	22.00
CQA cycles if FP arith vectorized	22.00
CQA cycles if fully vectorized	22.00
Front-end cycles	9.83
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	6.33
P5 cycles	6.33
P6 cycles	6.33
P7 cycles	22.00
P8 cycles	22.00
P9 cycles	12.00
P10 cycles	12.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	16.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	59.00
Nb loads	10.00
Nb stores	4.00
Nb stack references	3.00
FLOP/cycle	16.36
Nb FLOP add-sub	72.00
Nb FLOP mul	56.00
Nb FLOP fma	112.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.00
Bytes prefetched	0.00
Bytes loaded	360.00
Bytes stored	256.00
Stride 0	2.00
Stride 1	4.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	96.00
Vectorization ratio load	71.43
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	80.00
Vector-efficiency ratio all	96.50
Vector-efficiency ratio load	75.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	82.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P8, P9,
Function	_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE
Source	SoaDistanceTableABOMPTarget.h:228-228,ParticleBConds3DSoa.h:280-298
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	22.00
CQA cycles if no scalar integer	22.00
CQA cycles if FP arith vectorized	22.00
CQA cycles if fully vectorized	22.00
Front-end cycles	9.83
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	6.33
P5 cycles	6.33
P6 cycles	6.33
P7 cycles	22.00
P8 cycles	22.00
P9 cycles	12.00
P10 cycles	12.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	16.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	59.00
Nb loads	10.00
Nb stores	4.00
Nb stack references	3.00
FLOP/cycle	16.36
Nb FLOP add-sub	72.00
Nb FLOP mul	56.00
Nb FLOP fma	112.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.00
Bytes prefetched	0.00
Bytes loaded	360.00
Bytes stored	256.00
Stride 0	2.00
Stride 1	4.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	96.00
Vectorization ratio load	71.43
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	80.00
Vector-efficiency ratio all	96.50
Vector-efficiency ratio load	75.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	82.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE
Source file and lines	ParticleBConds3DSoa.h:280-298
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:228
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 96% of vector register length is used (average across all SSE/AVX instructions).

Details

96% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

71% of SSE/AVX loads are used in vector version.
80% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 112 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 4 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

34 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 360 FP arithmetical operations:

184: addition or subtraction (112 inside FMA instructions)
168: multiply (112 inside FMA instructions)
8: square root

The binary loop is loading 360 bytes (45 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.58 FP operations per loaded or stored byte.

General properties

nb instructions	56
nb uops	59
loop length	354
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	29
nb stack references	3
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.83 cycles
front end	9.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	4.67	4.67	4.67	11.00	11.00	7.50	7.50	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	6.33	6.33	6.33	22.00	22.00	12.00	12.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.83
Dispatch	22.00
DIV/SQRT	16.00
Data deps.	1.00
Overall L1	22.00

Vectorization ratios

INT

all	71%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	71%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	96%
load	71%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	80%

Vector efficiency ratios

INT

all	75%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	75%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	96%
load	75%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	82%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.00 cycles. At this rate:

17% of peak load performance is reached (16.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (11.64 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2e20d0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV -0x30(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVUPD (%RAX,%RDI,8),%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VPBROADCASTQ -0xddfad(%RIP),%ZMM31	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	5	0.50
VMOVUPD (%RCX,%RDI,8),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
MOV -0xb8(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VSUBPD %ZMM23,%ZMM26,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVDQA64 %ZMM31,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVDQA64 %ZMM31,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVUPD (%RCX,%RDI,8),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
MOV -0xb0(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VSUBPD %ZMM21,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM24,%ZMM0,%ZMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMULPD %ZMM24,%ZMM3,%ZMM28	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMULPD %ZMM24,%ZMM6,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VSUBPD %ZMM22,%ZMM25,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD231PD %ZMM25,%ZMM1,%ZMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM25,%ZMM4,%ZMM28	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM25,%ZMM7,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VPBROADCASTQ -0xddebd(%RIP),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	5	0.50
VFMADD231PD %ZMM26,%ZMM2,%ZMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM26,%ZMM5,%ZMM28	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM26,%ZMM8,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VPTERNLOGQ $-0x8,%ZMM25,%ZMM27,%ZMM29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VPTERNLOGQ $-0x8,%ZMM25,%ZMM28,%ZMM30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VPTERNLOGQ $-0x8,%ZMM25,%ZMM24,%ZMM31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VADDPD %ZMM29,%ZMM27,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM31,%ZMM24,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VRNDSCALEPD $0xb,%ZMM29,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VRNDSCALEPD $0xb,%ZMM25,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM29,%ZMM27,%ZMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM30,%ZMM28,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM25,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VRNDSCALEPD $0xb,%ZMM29,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM27,%ZMM12,%ZMM26	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VSUBPD %ZMM29,%ZMM28,%ZMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM27,%ZMM9,%ZMM29	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMULPD %ZMM27,%ZMM15,%ZMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD231PD %ZMM28,%ZMM10,%ZMM29	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM28,%ZMM13,%ZMM26	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM28,%ZMM16,%ZMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM11,%ZMM24,%ZMM29	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM24,%ZMM14,%ZMM26	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM24,%ZMM17,%ZMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVUPD %ZMM29,(%R8,%RDI,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM26,(%R9,%RDI,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM27,(%RCX,%RDI,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD (%R8,%RDI,8),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R9,%RDI,8),%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD %ZMM24,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD231PD %ZMM27,%ZMM27,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM26,%ZMM26,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VSQRTPD %ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	16
VMOVUPD %ZMM24,(%R14,%RDI,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
ADD $0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RDI,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 2e20d0 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x690>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE
Source file and lines	ParticleBConds3DSoa.h:280-298
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:228
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 96% of vector register length is used (average across all SSE/AVX instructions).

Details

96% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

71% of SSE/AVX loads are used in vector version.
80% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 112 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 4 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

34 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 360 FP arithmetical operations:

184: addition or subtraction (112 inside FMA instructions)
168: multiply (112 inside FMA instructions)
8: square root

The binary loop is loading 360 bytes (45 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.58 FP operations per loaded or stored byte.

General properties

nb instructions	56
nb uops	59
loop length	354
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	29
nb stack references	3
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.83 cycles
front end	9.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	4.67	4.67	4.67	11.00	11.00	7.50	7.50	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	6.33	6.33	6.33	22.00	22.00	12.00	12.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.83
Dispatch	22.00
DIV/SQRT	16.00
Data deps.	1.00
Overall L1	22.00

Vectorization ratios

INT

all	71%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	71%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	96%
load	71%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	80%

Vector efficiency ratios

INT

all	75%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	75%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	96%
load	75%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	82%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.00 cycles. At this rate:

17% of peak load performance is reached (16.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (11.64 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2e20d0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV -0x30(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVUPD (%RAX,%RDI,8),%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VPBROADCASTQ -0xddfad(%RIP),%ZMM31	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	5	0.50
VMOVUPD (%RCX,%RDI,8),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
MOV -0xb8(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VSUBPD %ZMM23,%ZMM26,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVDQA64 %ZMM31,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVDQA64 %ZMM31,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVUPD (%RCX,%RDI,8),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
MOV -0xb0(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VSUBPD %ZMM21,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM24,%ZMM0,%ZMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMULPD %ZMM24,%ZMM3,%ZMM28	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMULPD %ZMM24,%ZMM6,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VSUBPD %ZMM22,%ZMM25,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD231PD %ZMM25,%ZMM1,%ZMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM25,%ZMM4,%ZMM28	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM25,%ZMM7,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VPBROADCASTQ -0xddebd(%RIP),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	5	0.50
VFMADD231PD %ZMM26,%ZMM2,%ZMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM26,%ZMM5,%ZMM28	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM26,%ZMM8,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VPTERNLOGQ $-0x8,%ZMM25,%ZMM27,%ZMM29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VPTERNLOGQ $-0x8,%ZMM25,%ZMM28,%ZMM30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VPTERNLOGQ $-0x8,%ZMM25,%ZMM24,%ZMM31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VADDPD %ZMM29,%ZMM27,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM31,%ZMM24,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VRNDSCALEPD $0xb,%ZMM29,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VRNDSCALEPD $0xb,%ZMM25,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM29,%ZMM27,%ZMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM30,%ZMM28,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM25,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VRNDSCALEPD $0xb,%ZMM29,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM27,%ZMM12,%ZMM26	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VSUBPD %ZMM29,%ZMM28,%ZMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD %ZMM27,%ZMM9,%ZMM29	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMULPD %ZMM27,%ZMM15,%ZMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD231PD %ZMM28,%ZMM10,%ZMM29	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM28,%ZMM13,%ZMM26	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM28,%ZMM16,%ZMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM11,%ZMM24,%ZMM29	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM24,%ZMM14,%ZMM26	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM24,%ZMM17,%ZMM27	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVUPD %ZMM29,(%R8,%RDI,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM26,(%R9,%RDI,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM27,(%RCX,%RDI,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD (%R8,%RDI,8),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R9,%RDI,8),%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD %ZMM24,%ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD231PD %ZMM27,%ZMM27,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM26,%ZMM26,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VSQRTPD %ZMM24,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	16
VMOVUPD %ZMM24,(%R14,%RDI,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
ADD $0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RDI,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 2e20d0 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x690>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code