OV - exec - Loop 1310

	Loop Id: 1310	Module: exec	Source: ParticleBConds3DSoa.h:234-255	Coverage: 0.67%

0x289a00 MOVSXD	%R13D,%R13

0x289a03 VMOVDQA64	%ZMM7,%ZMM13

0x289a09 VMOVUPD	(%RDX,%R13,8),%ZMM8    [6]

0x289a10 VMOVUPD	(%R10,%R13,8),%ZMM9    [4]

0x289a17 VMOVUPD	(%RSI,%R13,8),%ZMM10    [8]

0x289a1e VSUBPD	%ZMM3,%ZMM8,%ZMM8

0x289a24 VSUBPD	%ZMM4,%ZMM9,%ZMM9

0x289a2a VMULPD	0x48(%RDI){1to8},%ZMM8,%ZMM11    [3]

0x289a31 VMULPD	0x60(%RDI){1to8},%ZMM8,%ZMM12    [3]

0x289a38 VSUBPD	%ZMM5,%ZMM10,%ZMM10

0x289a3e VMULPD	0x78(%RDI){1to8},%ZMM8,%ZMM8    [3]

0x289a45 VFMADD231PD	0x50(%RDI){1to8},%ZMM9,%ZMM11    [3]

0x289a4c VFMADD231PD	0x68(%RDI){1to8},%ZMM9,%ZMM12    [3]

0x289a53 VFMADD231PD	0x80(%RDI){1to8},%ZMM9,%ZMM8    [3]

0x289a5a VMOVDQA64	%ZMM7,%ZMM9

0x289a60 VFMADD231PD	0x58(%RDI){1to8},%ZMM10,%ZMM11    [3]

0x289a67 VFMADD231PD	0x70(%RDI){1to8},%ZMM10,%ZMM12    [3]

0x289a6e VFMADD231PD	0x88(%RDI){1to8},%ZMM10,%ZMM8    [3]

0x289a75 VMOVDQA64	%ZMM7,%ZMM10

0x289a7b VPTERNLOGQ	$-0x8,%ZMM6,%ZMM11,%ZMM9

0x289a82 VPTERNLOGQ	$-0x8,%ZMM6,%ZMM12,%ZMM10

0x289a89 VPTERNLOGQ	$-0x8,%ZMM6,%ZMM8,%ZMM13

0x289a90 VADDPD	%ZMM9,%ZMM11,%ZMM9

0x289a96 VADDPD	%ZMM10,%ZMM12,%ZMM10

0x289a9c VRNDSCALEPD	$0xb,%ZMM9,%ZMM9

0x289aa3 VRNDSCALEPD	$0xb,%ZMM10,%ZMM10

0x289aaa VSUBPD	%ZMM9,%ZMM11,%ZMM9

0x289ab0 VADDPD	%ZMM13,%ZMM8,%ZMM11

0x289ab6 VSUBPD	%ZMM10,%ZMM12,%ZMM10

0x289abc VMULPD	(%RDI){1to8},%ZMM9,%ZMM12    [3]

0x289ac2 VRNDSCALEPD	$0xb,%ZMM11,%ZMM11

0x289ac9 VFMADD231PD	0x8(%RDI){1to8},%ZMM10,%ZMM12    [3]

0x289ad0 VSUBPD	%ZMM11,%ZMM8,%ZMM8

0x289ad6 VFMADD231PD	0x10(%RDI){1to8},%ZMM8,%ZMM12    [3]

0x289add VMOVUPD	%ZMM12,(%R8,%R13,8)    [7]

0x289ae4 VMULPD	0x18(%RDI){1to8},%ZMM9,%ZMM11    [3]

0x289aeb VFMADD231PD	0x20(%RDI){1to8},%ZMM10,%ZMM11    [3]

0x289af2 VFMADD231PD	0x28(%RDI){1to8},%ZMM8,%ZMM11    [3]

0x289af9 VMOVUPD	%ZMM11,(%RBX,%R13,8)    [5]

0x289b00 VMULPD	0x30(%RDI){1to8},%ZMM9,%ZMM9    [3]

0x289b07 VFMADD231PD	0x38(%RDI){1to8},%ZMM10,%ZMM9    [3]

0x289b0e VFMADD231PD	0x40(%RDI){1to8},%ZMM8,%ZMM9    [3]

0x289b15 VMOVUPD	%ZMM9,(%R11,%R13,8)    [2]

0x289b1c VMOVUPD	(%R8,%R13,8),%ZMM8    [7]

0x289b23 VMOVUPD	(%RBX,%R13,8),%ZMM10    [5]

0x289b2a VMULPD	%ZMM8,%ZMM8,%ZMM8

0x289b30 VFMADD231PD	%ZMM9,%ZMM9,%ZMM8

0x289b36 VFMADD231PD	%ZMM10,%ZMM10,%ZMM8

0x289b3c VSQRTPD	%ZMM8,%ZMM8

0x289b42 VMOVUPD	%ZMM8,(%RCX,%R13,8)    [1]

0x289b49 ADD	$0x8,%R13D

0x289b4d ADD	$-0x8,%R12D

0x289b51 JNE	289a00

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 234 - 255

--------------------------------------------------------------------------------

234: #pragma omp simd aligned(temp_r, px, py, pz, dx, dy, dz: QMC_SIMD_ALIGNMENT)

235:     for (int iat = first; iat < last; ++iat)

236:     {

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	P8, P9,
Function	_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii
Source	ParticleBConds3DSoa.h:234-255
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	22.00
CQA cycles if no scalar integer	22.00
CQA cycles if FP arith vectorized	22.00
CQA cycles if fully vectorized	22.00
Front-end cycles	9.33
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	16.67
P5 cycles	16.67
P6 cycles	16.67
P7 cycles	22.00
P8 cycles	22.00
P9 cycles	12.00
P10 cycles	12.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	16.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	56.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	16.36
Nb FLOP add-sub	72.00
Nb FLOP mul	56.00
Nb FLOP fma	112.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.73
Bytes prefetched	0.00
Bytes loaded	464.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	P8, P9,
Function	_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii
Source	ParticleBConds3DSoa.h:234-255
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	22.00
CQA cycles if no scalar integer	22.00
CQA cycles if FP arith vectorized	22.00
CQA cycles if fully vectorized	22.00
Front-end cycles	9.33
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	16.67
P5 cycles	16.67
P6 cycles	16.67
P7 cycles	22.00
P8 cycles	22.00
P9 cycles	12.00
P10 cycles	12.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	16.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	56.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	16.36
Nb FLOP add-sub	72.00
Nb FLOP mul	56.00
Nb FLOP fma	112.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	8.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.73
Bytes prefetched	0.00
Bytes loaded	464.00
Bytes stored	256.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii
Source file and lines	ParticleBConds3DSoa.h:234-255
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:234-255.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 22.00 to 16.67 cycles (1.32x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 112 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 4 occurrences

Type of elements and instruction set

34 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 360 FP arithmetical operations:

184: addition or subtraction (112 inside FMA instructions)
168: multiply (112 inside FMA instructions)
8: square root

The binary loop is loading 464 bytes (58 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

General properties

nb instructions	53
nb uops	56
loop length	343
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	11
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.33 cycles
front end	9.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	9.00	9.00	9.00	11.00	11.00	7.50	7.50	4.00	4.00
cycles	0.75	0.75	0.50	0.50	0.50	16.67	16.67	16.67	22.00	22.00	12.00	12.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.33
Dispatch	22.00
DIV/SQRT	16.00
Data deps.	2.00
Overall L1	22.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.00 cycles. At this rate:

21% of peak load performance is reached (21.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (11.64 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 289a00

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOVSXD %R13D,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVDQA64 %ZMM7,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVUPD (%RDX,%R13,8),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R10,%R13,8),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%RSI,%R13,8),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VSUBPD %ZMM3,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM4,%ZMM9,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD 0x48(%RDI){1to8},%ZMM8,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0x60(%RDI){1to8},%ZMM8,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VSUBPD %ZMM5,%ZMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD 0x78(%RDI){1to8},%ZMM8,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD 0x50(%RDI){1to8},%ZMM9,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x68(%RDI){1to8},%ZMM9,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x80(%RDI){1to8},%ZMM9,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVDQA64 %ZMM7,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD 0x58(%RDI){1to8},%ZMM10,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x70(%RDI){1to8},%ZMM10,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x88(%RDI){1to8},%ZMM10,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVDQA64 %ZMM7,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPTERNLOGQ $-0x8,%ZMM6,%ZMM11,%ZMM9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VPTERNLOGQ $-0x8,%ZMM6,%ZMM12,%ZMM10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VPTERNLOGQ $-0x8,%ZMM6,%ZMM8,%ZMM13	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VADDPD %ZMM9,%ZMM11,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM10,%ZMM12,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VRNDSCALEPD $0xb,%ZMM9,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VRNDSCALEPD $0xb,%ZMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM9,%ZMM11,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM13,%ZMM8,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM10,%ZMM12,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD (%RDI){1to8},%ZMM9,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VRNDSCALEPD $0xb,%ZMM11,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD231PD 0x8(%RDI){1to8},%ZMM10,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VSUBPD %ZMM11,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD231PD 0x10(%RDI){1to8},%ZMM8,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVUPD %ZMM12,(%R8,%R13,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMULPD 0x18(%RDI){1to8},%ZMM9,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD 0x20(%RDI){1to8},%ZMM10,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x28(%RDI){1to8},%ZMM8,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVUPD %ZMM11,(%RBX,%R13,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMULPD 0x30(%RDI){1to8},%ZMM9,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD 0x38(%RDI){1to8},%ZMM10,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x40(%RDI){1to8},%ZMM8,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVUPD %ZMM9,(%R11,%R13,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD (%R8,%R13,8),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%RBX,%R13,8),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD %ZMM8,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD231PD %ZMM9,%ZMM9,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM10,%ZMM10,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VSQRTPD %ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	16
VMOVUPD %ZMM8,(%RCX,%R13,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
ADD $0x8,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $-0x8,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 289a00 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0xb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii
Source file and lines	ParticleBConds3DSoa.h:234-255
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 112 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 4 occurrences

Type of elements and instruction set

34 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 360 FP arithmetical operations:

184: addition or subtraction (112 inside FMA instructions)
168: multiply (112 inside FMA instructions)
8: square root

The binary loop is loading 464 bytes (58 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

General properties

nb instructions	53
nb uops	56
loop length	343
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	11
nb stack references	0
ADD-SUB / MUL ratio	1.29

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.33 cycles
front end	9.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	9.00	9.00	9.00	11.00	11.00	7.50	7.50	4.00	4.00
cycles	0.75	0.75	0.50	0.50	0.50	16.67	16.67	16.67	22.00	22.00	12.00	12.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.33
Dispatch	22.00
DIV/SQRT	16.00
Data deps.	2.00
Overall L1	22.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.00 cycles. At this rate:

21% of peak load performance is reached (21.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (11.64 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 289a00

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOVSXD %R13D,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVDQA64 %ZMM7,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVUPD (%RDX,%R13,8),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R10,%R13,8),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%RSI,%R13,8),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VSUBPD %ZMM3,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM4,%ZMM9,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD 0x48(%RDI){1to8},%ZMM8,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0x60(%RDI){1to8},%ZMM8,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VSUBPD %ZMM5,%ZMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD 0x78(%RDI){1to8},%ZMM8,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD 0x50(%RDI){1to8},%ZMM9,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x68(%RDI){1to8},%ZMM9,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x80(%RDI){1to8},%ZMM9,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVDQA64 %ZMM7,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD 0x58(%RDI){1to8},%ZMM10,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x70(%RDI){1to8},%ZMM10,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x88(%RDI){1to8},%ZMM10,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVDQA64 %ZMM7,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPTERNLOGQ $-0x8,%ZMM6,%ZMM11,%ZMM9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VPTERNLOGQ $-0x8,%ZMM6,%ZMM12,%ZMM10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VPTERNLOGQ $-0x8,%ZMM6,%ZMM8,%ZMM13	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
VADDPD %ZMM9,%ZMM11,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM10,%ZMM12,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VRNDSCALEPD $0xb,%ZMM9,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VRNDSCALEPD $0xb,%ZMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM9,%ZMM11,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM13,%ZMM8,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM10,%ZMM12,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMULPD (%RDI){1to8},%ZMM9,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VRNDSCALEPD $0xb,%ZMM11,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD231PD 0x8(%RDI){1to8},%ZMM10,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VSUBPD %ZMM11,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD231PD 0x10(%RDI){1to8},%ZMM8,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVUPD %ZMM12,(%R8,%R13,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMULPD 0x18(%RDI){1to8},%ZMM9,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD 0x20(%RDI){1to8},%ZMM10,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x28(%RDI){1to8},%ZMM8,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVUPD %ZMM11,(%RBX,%R13,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMULPD 0x30(%RDI){1to8},%ZMM9,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMADD231PD 0x38(%RDI){1to8},%ZMM10,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x40(%RDI){1to8},%ZMM8,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVUPD %ZMM9,(%R11,%R13,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD (%R8,%R13,8),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%RBX,%R13,8),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD %ZMM8,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD231PD %ZMM9,%ZMM9,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD %ZMM10,%ZMM10,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VSQRTPD %ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	16
VMOVUPD %ZMM8,(%RCX,%R13,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
ADD $0x8,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $-0x8,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 289a00 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm64EEEEES8_EEvRKT_RKT0_PdRT1_iii+0xb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code