OV - exec - Loop 1059

	Loop Id: 1059	Module: exec	Source: inner_product.hpp:155-155 [...]	Coverage: 0.3%

0x2744a0 VMOVUPD	(%R9),%ZMM24    [2]

0x2744a6 VMOVUPD	0x40(%R9),%ZMM23    [2]

0x2744ad VMOVUPD	0x80(%R9),%ZMM28    [2]

0x2744b4 VMOVUPD	-0xc0(%R12,%RDX,1),%ZMM27    [1]

0x2744bc VMOVUPD	-0x80(%R12,%RDX,1),%ZMM29    [1]

0x2744c4 VMOVAPD	%ZMM24,%ZMM25

0x2744ca VPERMT2PD	%ZMM23,%ZMM4,%ZMM25

0x2744d0 VMOVAPD	%ZMM24,%ZMM26

0x2744d6 VPERMT2PD	%ZMM23,%ZMM6,%ZMM26

0x2744dc VPERMT2PD	%ZMM24,%ZMM8,%ZMM23

0x2744e2 VPERMT2PD	%ZMM28,%ZMM5,%ZMM25

0x2744e8 VPERMT2PD	%ZMM28,%ZMM7,%ZMM26

0x2744ee VPERMT2PD	%ZMM28,%ZMM9,%ZMM23

0x2744f4 VMOVUPD	0xc0(%R9),%ZMM28    [2]

0x2744fb VFMADD231PD	%ZMM25,%ZMM27,%ZMM11

0x274501 VMOVUPD	0x100(%R9),%ZMM25    [2]

0x274508 VFMADD231PD	%ZMM23,%ZMM27,%ZMM19

0x27450e VFMADD231PD	%ZMM26,%ZMM27,%ZMM15

0x274514 VMOVUPD	0x140(%R9),%ZMM27    [2]

0x27451b VMOVAPD	%ZMM28,%ZMM23

0x274521 VMOVAPD	%ZMM28,%ZMM24

0x274527 VPERMT2PD	%ZMM25,%ZMM4,%ZMM23

0x27452d VPERMT2PD	%ZMM25,%ZMM6,%ZMM24

0x274533 VPERMT2PD	%ZMM28,%ZMM8,%ZMM25

0x274539 VMOVUPD	0x180(%R9),%ZMM28    [2]

0x274540 VPERMT2PD	%ZMM27,%ZMM5,%ZMM23

0x274546 VPERMT2PD	%ZMM27,%ZMM9,%ZMM25

0x27454c VPERMT2PD	%ZMM27,%ZMM7,%ZMM24

0x274552 VMOVUPD	0x200(%R9),%ZMM27    [2]

0x274559 VMOVAPD	%ZMM28,%ZMM26

0x27455f VFMADD231PD	%ZMM23,%ZMM29,%ZMM12

0x274565 VMOVUPD	0x1c0(%R9),%ZMM23    [2]

0x27456c VFMADD231PD	%ZMM25,%ZMM29,%ZMM20

0x274572 VMOVAPD	%ZMM28,%ZMM25

0x274578 VFMADD231PD	%ZMM24,%ZMM29,%ZMM16

0x27457e VPERMT2PD	%ZMM23,%ZMM4,%ZMM25

0x274584 VPERMT2PD	%ZMM23,%ZMM6,%ZMM26

0x27458a VPERMT2PD	%ZMM28,%ZMM8,%ZMM23

0x274590 VMOVUPD	-0x40(%R12,%RDX,1),%ZMM28    [1]

0x274598 VPERMT2PD	%ZMM27,%ZMM5,%ZMM25

0x27459e VPERMT2PD	%ZMM27,%ZMM7,%ZMM26

0x2745a4 VPERMT2PD	%ZMM27,%ZMM9,%ZMM23

0x2745aa VMOVUPD	0x240(%R9),%ZMM27    [2]

0x2745b1 VFMADD231PD	%ZMM25,%ZMM28,%ZMM13

0x2745b7 VMOVUPD	0x280(%R9),%ZMM25    [2]

0x2745be VFMADD231PD	%ZMM23,%ZMM28,%ZMM21

0x2745c4 VFMADD231PD	%ZMM26,%ZMM28,%ZMM17

0x2745ca VMOVUPD	0x2c0(%R9),%ZMM28    [2]

0x2745d1 ADD	$0x300,%R9

0x2745d8 VMOVAPD	%ZMM27,%ZMM23

0x2745de VMOVAPD	%ZMM27,%ZMM24

0x2745e4 VPERMT2PD	%ZMM25,%ZMM4,%ZMM23

0x2745ea VPERMT2PD	%ZMM25,%ZMM6,%ZMM24

0x2745f0 VPERMT2PD	%ZMM27,%ZMM8,%ZMM25

0x2745f6 VMOVUPD	(%R12,%RDX,1),%ZMM27    [1]

0x2745fd ADD	$0x100,%RDX

0x274604 VPERMT2PD	%ZMM28,%ZMM5,%ZMM23

0x27460a VPERMT2PD	%ZMM28,%ZMM7,%ZMM24

0x274610 VPERMT2PD	%ZMM28,%ZMM9,%ZMM25

0x274616 VFMADD231PD	%ZMM23,%ZMM27,%ZMM14

0x27461c VFMADD231PD	%ZMM24,%ZMM27,%ZMM18

0x274622 VFMADD231PD	%ZMM25,%ZMM27,%ZMM22

0x274628 CMP	%RDX,%R13

0x27462b JNE	2744a0

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 155 - 155

--------------------------------------------------------------------------------

155:   for (int i = 0; i < n; i++)

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 63 - 94

--------------------------------------------------------------------------------

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.25
Bottlenecks	P8, P9, P10,
Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb
Source	inner_product.hpp:155-155,OperatorTags.h:63-63,OperatorTags.h:94-94
Source loop unroll info	unrolled by 24
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	24
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	24.00
Front-end cycles	10.50
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	10.67
P5 cycles	10.67
P6 cycles	10.67
P7 cycles	24.00
P8 cycles	24.00
P9 cycles	24.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	63.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	96.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.67
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.25
Bottlenecks	P8, P9, P10,
Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb
Source	inner_product.hpp:155-155,OperatorTags.h:63-63,OperatorTags.h:94-94
Source loop unroll info	unrolled by 24
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	24
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	24.00
Front-end cycles	10.50
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	10.67
P5 cycles	10.67
P6 cycles	10.67
P7 cycles	24.00
P8 cycles	24.00
P9 cycles	24.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	63.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	96.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.67
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb
Source file and lines	inner_product.hpp:155-155
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94

It is main loop of related source loop which is unrolled by 24 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 24.00 to 10.67 cycles (2.25x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 96 FMA (fused multiply-add) operations.

Type of elements and instruction set

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

96: addition or subtraction (all inside FMA instructions)
96: multiply (all inside FMA instructions)

The binary loop is loading 1024 bytes (128 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	64
nb uops	63
loop length	401
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	25
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	5.33	5.33	5.33	12.00	24.00	24.00	0.00	0.00	0.00
cycles	0.75	0.75	0.50	0.50	0.50	10.67	10.67	10.67	24.00	24.00	24.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	10.50
Dispatch	24.00
Data deps.	4.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

44% of peak load performance is reached (42.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2744a0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	Latency	Recip. throughput
VMOVUPD (%R9),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0x40(%R9),%ZMM23	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0x80(%R9),%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD -0xc0(%R12,%RDX,1),%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD -0x80(%R12,%RDX,1),%ZMM29	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVAPD %ZMM24,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM23,%ZMM4,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVAPD %ZMM24,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM23,%ZMM6,%ZMM26	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM24,%ZMM8,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM28,%ZMM5,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM28,%ZMM7,%ZMM26	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM28,%ZMM9,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0xc0(%R9),%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM25,%ZMM27,%ZMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x100(%R9),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM23,%ZMM27,%ZMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VFMADD231PD %ZMM26,%ZMM27,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x140(%R9),%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVAPD %ZMM28,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD %ZMM28,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM25,%ZMM4,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM6,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM28,%ZMM8,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0x180(%R9),%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM27,%ZMM5,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM27,%ZMM9,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM27,%ZMM7,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0x200(%R9),%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVAPD %ZMM28,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD %ZMM23,%ZMM29,%ZMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x1c0(%R9),%ZMM23	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM25,%ZMM29,%ZMM20	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVAPD %ZMM28,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD %ZMM24,%ZMM29,%ZMM16	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VPERMT2PD %ZMM23,%ZMM4,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM23,%ZMM6,%ZMM26	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM28,%ZMM8,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD -0x40(%R12,%RDX,1),%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM27,%ZMM5,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM27,%ZMM7,%ZMM26	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM27,%ZMM9,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0x240(%R9),%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM25,%ZMM28,%ZMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x280(%R9),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM23,%ZMM28,%ZMM21	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VFMADD231PD %ZMM26,%ZMM28,%ZMM17	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x2c0(%R9),%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
ADD $0x300,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
VMOVAPD %ZMM27,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD %ZMM27,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM25,%ZMM4,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM6,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM27,%ZMM8,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD (%R12,%RDX,1),%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
ADD $0x100,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
VPERMT2PD %ZMM28,%ZMM5,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM28,%ZMM7,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM28,%ZMM9,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD231PD %ZMM23,%ZMM27,%ZMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VFMADD231PD %ZMM24,%ZMM27,%ZMM18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VFMADD231PD %ZMM25,%ZMM27,%ZMM22	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
CMP %RDX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JNE 2744a0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x430>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb
Source file and lines	inner_product.hpp:155-155
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94

It is main loop of related source loop which is unrolled by 24 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 96 FMA (fused multiply-add) operations.

Type of elements and instruction set

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

96: addition or subtraction (all inside FMA instructions)
96: multiply (all inside FMA instructions)

The binary loop is loading 1024 bytes (128 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	64
nb uops	63
loop length	401
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	25
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	5.33	5.33	5.33	12.00	24.00	24.00	0.00	0.00	0.00
cycles	0.75	0.75	0.50	0.50	0.50	10.67	10.67	10.67	24.00	24.00	24.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	10.50
Dispatch	24.00
Data deps.	4.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

44% of peak load performance is reached (42.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2744a0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	Latency	Recip. throughput
VMOVUPD (%R9),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0x40(%R9),%ZMM23	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0x80(%R9),%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD -0xc0(%R12,%RDX,1),%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD -0x80(%R12,%RDX,1),%ZMM29	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVAPD %ZMM24,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM23,%ZMM4,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVAPD %ZMM24,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM23,%ZMM6,%ZMM26	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM24,%ZMM8,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM28,%ZMM5,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM28,%ZMM7,%ZMM26	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM28,%ZMM9,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0xc0(%R9),%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM25,%ZMM27,%ZMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x100(%R9),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM23,%ZMM27,%ZMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VFMADD231PD %ZMM26,%ZMM27,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x140(%R9),%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVAPD %ZMM28,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD %ZMM28,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM25,%ZMM4,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM6,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM28,%ZMM8,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0x180(%R9),%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM27,%ZMM5,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM27,%ZMM9,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM27,%ZMM7,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0x200(%R9),%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVAPD %ZMM28,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD %ZMM23,%ZMM29,%ZMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x1c0(%R9),%ZMM23	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM25,%ZMM29,%ZMM20	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVAPD %ZMM28,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD %ZMM24,%ZMM29,%ZMM16	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VPERMT2PD %ZMM23,%ZMM4,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM23,%ZMM6,%ZMM26	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM28,%ZMM8,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD -0x40(%R12,%RDX,1),%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM27,%ZMM5,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM27,%ZMM7,%ZMM26	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM27,%ZMM9,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0x240(%R9),%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM25,%ZMM28,%ZMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x280(%R9),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM23,%ZMM28,%ZMM21	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VFMADD231PD %ZMM26,%ZMM28,%ZMM17	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x2c0(%R9),%ZMM28	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
ADD $0x300,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
VMOVAPD %ZMM27,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD %ZMM27,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM25,%ZMM4,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM6,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM27,%ZMM8,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD (%R12,%RDX,1),%ZMM27	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
ADD $0x100,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
VPERMT2PD %ZMM28,%ZMM5,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM28,%ZMM7,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM28,%ZMM9,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD231PD %ZMM23,%ZMM27,%ZMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VFMADD231PD %ZMM24,%ZMM27,%ZMM18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VFMADD231PD %ZMM25,%ZMM27,%ZMM22	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
CMP %RDX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JNE 2744a0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x430>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code