OV - exec - Function _ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS

	Function: _ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE	Module: exec	Source: WaveFunction.cpp:194-203 [...]	Coverage: 0.01%

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 164 - 164

--------------------------------------------------------------------------------

164:       X[d] = rhs;

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp: 194 - 203

--------------------------------------------------------------------------------

194: {

195:   grad       = valT(0);

196:   valT ratio = (iat < nelup ? Det_up->ratioGrad(P, iat, grad) : Det_dn->ratioGrad(P, iat, grad));

197:

198:   for (size_t i = 0; i < Jastrows.size(); i++)

199:   {

200:     ScopedTimer local_timer(jastrow_timers[i]);

201:     ratio *= Jastrows[i]->ratioGrad(P, iat, grad);

202:   }

203:   return ratio;

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 919 - 1046

--------------------------------------------------------------------------------

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1046: 	return *(this->_M_impl._M_start + __n);

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/refwrap.h: 338 - 338

--------------------------------------------------------------------------------

338:       { return *_M_data; }

0x22faa0 PUSH	%RBP

0x22faa1 MOV	%RSP,%RBP

0x22faa4 PUSH	%R15

0x22faa6 PUSH	%R14

0x22faa8 PUSH	%R13

0x22faaa PUSH	%R12

0x22faac PUSH	%RBX

0x22faad SUB	$0x18,%RSP

0x22fab1 VXORPD	%XMM0,%XMM0,%XMM0

0x22fab5 MOVQ	$0,0x10(%RCX)

0x22fabd XOR	%EAX,%EAX

0x22fabf MOV	%RDI,%R12

0x22fac2 MOV	%RCX,%RBX

0x22fac5 MOV	%EDX,%R14D

0x22fac8 MOV	%RSI,-0x38(%RBP)

0x22facc VMOVUPD	%XMM0,(%RCX)

0x22fad0 CMP	%EDX,0x34(%RDI)

0x22fad3 SETLE	%AL

0x22fad6 MOV	(%RDI,%RAX,8),%RDI

0x22fada MOV	(%RDI),%RAX

0x22fadd CALLQ	0x20(%RAX)

0x22fae0 MOV	0x18(%R12),%RAX

0x22fae5 VMOVSD	%XMM0,-0x30(%RBP)

0x22faea CMP	%RAX,0x10(%R12)

0x22faef JE	22fb5c

0x22faf1 XOR	%R15D,%R15D

0x22faf4 NOPW	%CS:(%RAX,%RAX,1)

(108) 0x22fb00 MOV	0x58(%R12),%RAX

(108) 0x22fb05 MOV	(%RAX,%R15,8),%R13

(108) 0x22fb09 MOV	%R13,%RDI

(108) 0x22fb0c CALL	2a0a60 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

(108) 0x22fb11 MOV	0x10(%R12),%RAX

(108) 0x22fb16 MOV	(%RAX,%R15,8),%RDI

(108) 0x22fb1a MOV	(%RDI),%RAX

(108) 0x22fb1d MOV	-0x38(%RBP),%RSI

(108) 0x22fb21 MOV	%R14D,%EDX

(108) 0x22fb24 MOV	%RBX,%RCX

(108) 0x22fb27 CALLQ	0x20(%RAX)

(108) 0x22fb2a VMOVSD	%XMM0,-0x40(%RBP)

(108) 0x22fb2f MOV	%R13,%RDI

(108) 0x22fb32 CALL	2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

(108) 0x22fb37 VMOVSD	-0x30(%RBP),%XMM0

(108) 0x22fb3c MOV	0x18(%R12),%RAX

(108) 0x22fb41 INC	%R15

(108) 0x22fb44 VMULSD	-0x40(%RBP),%XMM0,%XMM0

(108) 0x22fb49 SUB	0x10(%R12),%RAX

(108) 0x22fb4e SAR	$0x3,%RAX

(108) 0x22fb52 VMOVSD	%XMM0,-0x30(%RBP)

(108) 0x22fb57 CMP	%RAX,%R15

(108) 0x22fb5a JB	22fb00

0x22fb5c VMOVSD	-0x30(%RBP),%XMM0

0x22fb61 ADD	$0x18,%RSP

0x22fb65 POP	%RBX

0x22fb66 POP	%R12

0x22fb68 POP	%R13

0x22fb6a POP	%R14

0x22fb6c POP	%R15

0x22fb6e POP	%RBP

0x22fb6f RET

0x22fb70 MOV	%RAX,%RDI

0x22fb73 CALL	22b060 <__clang_call_terminate>

0x22fb78 MOV	%RAX,%RBX

0x22fb7b MOV	%R13,%RDI

0x22fb7e CALL	2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x22fb83 MOV	%RBX,%RDI

0x22fb86 CALL	2f6620 <@plt_start@+0x50>

0x22fb8b MOV	%RAX,%RDI

0x22fb8e CALL	22b060 <__clang_call_terminate>

0x22fb93 NOPW	%CS:(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	WaveFunction.cpp:194-203
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:164
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:194-203
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/refwrap.h:338

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.50 to 1.17 cycles (7.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 8.50 to 0.90 cycles (9.49x speedup).

Details

16% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.
14% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv: 1 occurrences
__clang_call_terminate: 2 occurrences
unknown: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	46
nb uops	51
loop length	164
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.00	1.50	1.50	1.50	3.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	1.00	1.00
cycles	4.00	1.50	1.50	1.50	3.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.50
Dispatch	5.33
Overall L1	8.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	16%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	9%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	18%
load	12%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	10%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.50 cycles. At this rate:

6% of peak load performance is reached (6.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.71 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.50 to 5.33 cycles (1.59x speedup).

ASM code

In the binary file, the address of the function is: 22faa0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVQ $0,0x10(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVUPD %XMM0,(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
CMP %EDX,0x34(%RDI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
SETLE %AL	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
MOV (%RDI,%RAX,8),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CALLQ 0x20(%RAX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	0	0	2.20
MOV 0x18(%R12),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVSD %XMM0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
CMP %RAX,0x10(%R12)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JE 22fb5c <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE+0xbc>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VMOVSD -0x30(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 22b060 <__clang_call_terminate>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2f6620 <@plt_start@+0x50>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 22b060 <__clang_call_terminate>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	WaveFunction.cpp:194-203
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:164
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/WaveFunction.cpp:194-203
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/refwrap.h:338

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.50 to 1.17 cycles (7.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

16% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.
14% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv: 1 occurrences
__clang_call_terminate: 2 occurrences
unknown: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	46
nb uops	51
loop length	164
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.00	1.50	1.50	1.50	3.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	1.00	1.00
cycles	4.00	1.50	1.50	1.50	3.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.50
Dispatch	5.33
Overall L1	8.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	16%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	9%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	18%
load	12%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	10%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.50 cycles. At this rate:

6% of peak load performance is reached (6.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.71 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 22faa0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVQ $0,0x10(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVUPD %XMM0,(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
CMP %EDX,0x34(%RDI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
SETLE %AL	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
MOV (%RDI,%RAX,8),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CALLQ 0x20(%RAX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	0	0	2.20
MOV 0x18(%R12),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVSD %XMM0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
CMP %RAX,0x10(%R12)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JE 22fb5c <_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE+0xbc>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VMOVSD -0x30(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 22b060 <__clang_call_terminate>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2f6620 <@plt_start@+0x50>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 22b060 <__clang_call_terminate>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Name	Coverage (%)	Time (s)
▼_ZN11qmcplusplus12WaveFunction9ratioGradERNS_11ParticleSetEiRNS_10TinyVectorIdLj3EEE–	0.01	0.01
○Loop 108 - WaveFunction.cpp:198-201 - exec	0	0.01

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Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code