OV - exec - Function _ZN16miniqmcreference17einspline_spo_refIdE10evaluate

	Function: _ZN16miniqmcreference17einspline_spo_refIdE10evaluate_vERKN11qmcplusplus11ParticleSetEi	Module: exec	Source: einspline_spo_ref.hpp:171-177 [...]	Coverage: 0.06%

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 143 - 143

--------------------------------------------------------------------------------

143:     return (active_ptcl_ == iat) ? active_pos_ : R[iat];

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1169

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

[...]

1169:       { return _M_data_ptr(this->_M_impl._M_start); }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h: 150 - 151

--------------------------------------------------------------------------------

150:     return TinyVector<Type_t, 3>(lhs[0] * rhs[0] + lhs[1] * rhs[3] + lhs[2] * rhs[6],

151:                                  lhs[0] * rhs[1] + lhs[1] * rhs[4] + lhs[2] * rhs[7],

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 171 - 177

--------------------------------------------------------------------------------

171:   {

172:     ScopedTimer local_timer(timer);

173:

174:     auto u = Lattice.toUnit_floor(P.activeR(iat));

175:     for (int i = 0; i < nBlocks; ++i)

176:       MultiBsplineEvalRef::evaluate_v(einsplines[i], u[0], u[1], u[2], psi[i].data(), nSplinesPerBlock);

177:   }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h: 170 - 170

--------------------------------------------------------------------------------

170:       if (-std::numeric_limits<T1>::epsilon() < val_dot[i] && val_dot[i] < 0)

0x25b570 PUSH	%RBP

0x25b571 MOV	%RSP,%RBP

0x25b574 PUSH	%R15

0x25b576 PUSH	%R14

0x25b578 PUSH	%R12

0x25b57a PUSH	%RBX

0x25b57b SUB	$0x30,%RSP

0x25b57f MOV	0x358(%RDI),%RBX

0x25b586 MOV	%RDI,%R14

0x25b589 MOV	%EDX,%R15D

0x25b58c MOV	%RSI,%R12

0x25b58f MOV	%RBX,%RDI

0x25b592 CALL	2a0a60 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x25b597 MOVSXD	%R15D,%RCX

0x25b59a LEA	0x128(%R12),%RDX

0x25b5a2 LEA	(%RCX,%RCX,2),%RAX

0x25b5a6 SAL	$0x3,%RAX

0x25b5aa ADD	0x40(%R12),%RAX

0x25b5af CMP	%ECX,0x124(%R12)

0x25b5b7 CMOVE	%RDX,%RAX

0x25b5bb CMPL	$0,0x30(%R14)

0x25b5c0 JLE	25b6de

0x25b5c6 VMOVUPD	0x100(%R14),%XMM2

0x25b5cf VMOVUPD	0x8(%RAX),%XMM1

0x25b5d4 VMOVSD	(%RAX),%XMM0

0x25b5d8 XOR	%R15D,%R15D

0x25b5db XOR	%R12D,%R12D

0x25b5de VMOVHPD	0x118(%R14),%XMM2,%XMM2

0x25b5e7 VMULPD	%XMM1,%XMM2,%XMM2

0x25b5eb VPERMILPD	$0x1,%XMM2,%XMM3

0x25b5f1 VFMADD231SD	0xe8(%R14),%XMM0,%XMM2

0x25b5fa VADDSD	%XMM3,%XMM2,%XMM2

0x25b5fe VROUNDSD	$0x9,%XMM2,%XMM2,%XMM3

0x25b604 VSUBSD	%XMM3,%XMM2,%XMM5

0x25b608 VXORPD	%XMM3,%XMM3,%XMM3

0x25b60c VCMPSD	$0x1,%XMM3,%XMM2,%K1

0x25b613 VMOVAPD	%XMM5,%XMM4

0x25b617 VMOVSD	%XMM3,%XMM4,%XMM4{%K1}

0x25b61d VCMPSD	$0xe,-0x574b8(%RIP),%XMM2,%K1

0x25b628 VMOVDDUP	%XMM1,%XMM2

0x25b62c VPERMILPD	$0x3,%XMM1,%XMM1

0x25b632 VMOVSD	%XMM4,%XMM5,%XMM5{%K1}

0x25b638 VMOVDDUP	%XMM0,%XMM0

0x25b63c VMULPD	0xd8(%R14),%XMM0,%XMM0

0x25b645 VMOVAPD	%XMM5,-0x50(%RBP)

0x25b64a VFMADD231PD	0xf0(%R14),%XMM2,%XMM0

0x25b653 VFMADD132PD	0x108(%R14),%XMM0,%XMM1

0x25b65c VXORPD	%XMM0,%XMM0,%XMM0

0x25b660 VCMPPD	$0x1,%XMM0,%XMM1,%K1

0x25b667 VCMPPD	$0xe,-0x57502(%RIP){1to0},%XMM1,%K0{%K1}

0x25b672 VROUNDPD	$0x9,%XMM1,%XMM0

0x25b678 KNOTW	%K0,%K1

0x25b67c VSUBPD	%XMM0,%XMM1,%XMM0{%K1}{z}

0x25b682 VMOVAPD	%XMM0,-0x40(%RBP)

0x25b687 VPERMILPD	$0x1,%XMM0,%XMM0

0x25b68d VMOVAPD	%XMM0,-0x30(%RBP)

0x25b692 NOPW	%CS:(%RAX,%RAX,1)

(839) 0x25b6a0 MOV	0x2f8(%R14),%RAX

(839) 0x25b6a7 MOV	0x310(%R14),%RCX

(839) 0x25b6ae MOVSXD	0x40(%R14),%RDX

(839) 0x25b6b2 MOV	(%RAX,%R12,8),%RDI

(839) 0x25b6b6 MOV	(%RCX,%R15,1),%RSI

(839) 0x25b6ba VMOVAPD	-0x40(%RBP),%XMM0

(839) 0x25b6bf VMOVAPD	-0x30(%RBP),%XMM1

(839) 0x25b6c4 VMOVAPD	-0x50(%RBP),%XMM2

(839) 0x25b6c9 CALL	25b720 <_ZN16miniqmcreference19MultiBsplineEvalRef10evaluate_vIdEEvPKN11qmcplusplus14bspline_traitsIT_Lj3EE10SplineTypeES4_S4_S4_PS4_m>

(839) 0x25b6ce MOVSXD	0x30(%R14),%RAX

(839) 0x25b6d2 INC	%R12

(839) 0x25b6d5 ADD	$0x18,%R15

(839) 0x25b6d9 CMP	%RAX,%R12

(839) 0x25b6dc JL	25b6a0

0x25b6de MOV	%RBX,%RDI

0x25b6e1 CALL	2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x25b6e6 ADD	$0x30,%RSP

0x25b6ea POP	%RBX

0x25b6eb POP	%R12

0x25b6ed POP	%R14

0x25b6ef POP	%R15

0x25b6f1 POP	%RBP

0x25b6f2 RET

0x25b6f3 MOV	%RAX,%RDI

0x25b6f6 CALL	22b060 <__clang_call_terminate>

0x25b6fb MOV	%RAX,%R14

0x25b6fe MOV	%RBX,%RDI

0x25b701 CALL	2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x25b706 MOV	%R14,%RDI

0x25b709 CALL	2f6620 <@plt_start@+0x50>

0x25b70e MOV	%RAX,%RDI

0x25b711 CALL	22b060 <__clang_call_terminate>

0x25b716 INT	$0x3

0x25b717 INT	$0x3

0x25b718 INT	$0x3

0x25b719 INT	$0x3

0x25b71a INT	$0x3

0x25b71b INT	$0x3

0x25b71c INT	$0x3

0x25b71d INT	$0x3

0x25b71e INT	$0x3

0x25b71f INT	$0x3

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	einspline_spo_ref.hpp:171-177
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046,1169
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-151
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:171-177
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.67 to 6.17 cycles (2.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 13.67 to 1.96 cycles (6.98x speedup).

Details

52% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

46% of SSE/AVX loads are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
66% of SSE/AVX fused multiply-add instructions are used in vector version.
45% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 5 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv: 2 occurrences
_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv: 1 occurrences
__clang_call_terminate: 2 occurrences
unknown: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCMPPD: 1 occurrences
VCMPSD: 1 occurrences

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (5 inside FMA instructions)
9: multiply (5 inside FMA instructions)

The binary function is loading 144 bytes (18 double precision FP elements). The binary function is storing 48 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	85
nb uops	82
loop length	370
used x86 registers	11
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	1.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.67 cycles
front end	13.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.50	3.25	3.25	3.00	4.00	7.67	7.67	7.67	5.75	5.75	5.67	5.83	1.50	1.50
cycles	4.50	3.25	3.25	3.00	4.00	7.67	7.67	7.67	5.75	5.75	5.67	5.83	1.50	1.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.67
Dispatch	7.67
Overall L1	13.67

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	61%
load	60%
store	100%
mul	100%
add-sub	33%
fma	66%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	56%

INT+FP

all	52%
load	46%
store	100%
mul	100%
add-sub	33%
fma	66%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

Vector efficiency ratios

INT

all	7%
load	8%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	20%
load	20%
store	25%
mul	25%
add-sub	16%
fma	20%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

INT+FP

all	18%
load	17%
store	25%
mul	25%
add-sub	16%
fma	20%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 13.67 cycles. At this rate:

10% of peak load performance is reached (10.54 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.51 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.67 to 7.67 cycles (1.78x speedup).

ASM code

In the binary file, the address of the function is: 25b570

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x30,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x358(%RDI),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EDX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2a0a60 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVSXD %R15D,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x128(%R12),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RCX,%RCX,2),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SAL $0x3,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD 0x40(%R12),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
CMP %ECX,0x124(%R12)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
CMOVE %RDX,%RAX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
CMPL $0,0x30(%R14)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JLE 25b6de <_ZN16miniqmcreference17einspline_spo_refIdE10evaluate_vERKN11qmcplusplus11ParticleSetEi+0x16e>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVUPD 0x100(%R14),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVUPD 0x8(%RAX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVSD (%RAX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
VMOVHPD 0x118(%R14),%XMM2,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMULPD %XMM1,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VPERMILPD $0x1,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VFMADD231SD 0xe8(%R14),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VADDSD %XMM3,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VROUNDSD $0x9,%XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM3,%XMM2,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VCMPSD $0x1,%XMM3,%XMM2,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVAPD %XMM5,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD %XMM3,%XMM4,%XMM4{%K1}	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VCMPSD $0xe,-0x574b8(%RIP),%XMM2,%K1	2	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VMOVDDUP %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VPERMILPD $0x3,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VMOVSD %XMM4,%XMM5,%XMM5{%K1}	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVDDUP %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VMULPD 0xd8(%R14),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VMOVAPD %XMM5,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VFMADD231PD 0xf0(%R14),%XMM2,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VFMADD132PD 0x108(%R14),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VCMPPD $0x1,%XMM0,%XMM1,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VCMPPD $0xe,-0x57502(%RIP){1to0},%XMM1,%K0{%K1}	2	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VROUNDPD $0x9,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
KNOTW %K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VSUBPD %XMM0,%XMM1,%XMM0{%K1}{z}	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVAPD %XMM0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VPERMILPD $0x1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VMOVAPD %XMM0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x30,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 22b060 <__clang_call_terminate>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2f6620 <@plt_start@+0x50>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 22b060 <__clang_call_terminate>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3

Source file and lines	einspline_spo_ref.hpp:171-177
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046,1169
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-151
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:171-177
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.67 to 6.17 cycles (2.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

52% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

46% of SSE/AVX loads are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
66% of SSE/AVX fused multiply-add instructions are used in vector version.
45% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 5 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv: 2 occurrences
_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv: 1 occurrences
__clang_call_terminate: 2 occurrences
unknown: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCMPPD: 1 occurrences
VCMPSD: 1 occurrences

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (5 inside FMA instructions)
9: multiply (5 inside FMA instructions)

The binary function is loading 144 bytes (18 double precision FP elements). The binary function is storing 48 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	85
nb uops	82
loop length	370
used x86 registers	11
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	1.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.67 cycles
front end	13.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.50	3.25	3.25	3.00	4.00	7.67	7.67	7.67	5.75	5.75	5.67	5.83	1.50	1.50
cycles	4.50	3.25	3.25	3.00	4.00	7.67	7.67	7.67	5.75	5.75	5.67	5.83	1.50	1.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.67
Dispatch	7.67
Overall L1	13.67

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	61%
load	60%
store	100%
mul	100%
add-sub	33%
fma	66%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	56%

INT+FP

all	52%
load	46%
store	100%
mul	100%
add-sub	33%
fma	66%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

Vector efficiency ratios

INT

all	7%
load	8%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	20%
load	20%
store	25%
mul	25%
add-sub	16%
fma	20%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

INT+FP

all	18%
load	17%
store	25%
mul	25%
add-sub	16%
fma	20%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 13.67 cycles. At this rate:

10% of peak load performance is reached (10.54 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.51 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 25b570

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x30,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x358(%RDI),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EDX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2a0a60 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVSXD %R15D,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x128(%R12),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RCX,%RCX,2),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SAL $0x3,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD 0x40(%R12),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
CMP %ECX,0x124(%R12)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
CMOVE %RDX,%RAX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
CMPL $0,0x30(%R14)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JLE 25b6de <_ZN16miniqmcreference17einspline_spo_refIdE10evaluate_vERKN11qmcplusplus11ParticleSetEi+0x16e>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVUPD 0x100(%R14),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVUPD 0x8(%RAX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVSD (%RAX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
VMOVHPD 0x118(%R14),%XMM2,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMULPD %XMM1,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VPERMILPD $0x1,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VFMADD231SD 0xe8(%R14),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VADDSD %XMM3,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VROUNDSD $0x9,%XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM3,%XMM2,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VCMPSD $0x1,%XMM3,%XMM2,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVAPD %XMM5,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD %XMM3,%XMM4,%XMM4{%K1}	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VCMPSD $0xe,-0x574b8(%RIP),%XMM2,%K1	2	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VMOVDDUP %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VPERMILPD $0x3,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VMOVSD %XMM4,%XMM5,%XMM5{%K1}	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVDDUP %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VMULPD 0xd8(%R14),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VMOVAPD %XMM5,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VFMADD231PD 0xf0(%R14),%XMM2,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VFMADD132PD 0x108(%R14),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VCMPPD $0x1,%XMM0,%XMM1,%K1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VCMPPD $0xe,-0x57502(%RIP){1to0},%XMM1,%K0{%K1}	2	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VROUNDPD $0x9,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
KNOTW %K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VSUBPD %XMM0,%XMM1,%XMM0{%K1}{z}	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVAPD %XMM0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VPERMILPD $0x1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VMOVAPD %XMM0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x30,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 22b060 <__clang_call_terminate>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2a0b50 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2f6620 <@plt_start@+0x50>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 22b060 <__clang_call_terminate>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3

Name	Coverage (%)	Time (s)
▼_ZN16miniqmcreference17einspline_spo_refIdE10evaluate_vERKN11qmcplusplus11ParticleSetEi–	0.06	0.12
○Loop 839 - einspline_spo_ref.hpp:175-176 - exec	0.02	0.03

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Masked instructions

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FMA

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CALL instructions

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

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Cycles summary

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Vector efficiency ratios

Cycles and memory resources usage

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