OV - exec - Function _ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd

	Function: _ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd	Module: exec	Source: OhmmsVector.h:182-302 [...]	Coverage: 0.01%

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h: 111 - 145

--------------------------------------------------------------------------------

111: 	if (__builtin_expect(__n > this->_M_max_size(), false))

112: 	  {

113: 	    // _GLIBCXX_RESOLVE_LIB_DEFECTS

114: 	    // 3190. allocator::allocate sometimes returns too little storage

115: 	    if (__n > (std::size_t(-1) / sizeof(_Tp)))

116: 	      std::__throw_bad_array_new_length();

117: 	    std::__throw_bad_alloc();

[...]

127: 	return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp)));

[...]

145: 	::operator delete(__p

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 182 - 302

--------------------------------------------------------------------------------

182:   {

183:     static_assert(std::is_same<value_type, typename Alloc::value_type>::value,

184:                   "Vector and Alloc data types must agree!");

185:     if (nLocal > nAllocated)

186:       throw std::runtime_error("Resize not allowed on Vector constructed by initialized memory.");

187:

188:     if (n > nAllocated)

[...]

195:       if (n > nLocal)

196:         qmc_allocator_traits<Alloc>::fill_n(X + nLocal, n - nLocal, val);

197:       nLocal = n;

198:     }

199:     return;

[...]

296:     if (nAllocated)

297:     {

298:       mAllocator.deallocate(X, nAllocated);

299:     }

300:     X          = mAllocator.allocate(n);

301:     nLocal     = n;

302:     nAllocated = n;

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 923 - 1120

--------------------------------------------------------------------------------

923:       for (; __first != __last; ++__first)

924: 	*__first = __tmp;

[...]

1120:       std::__fill_a(__first, __first + __n, __value);

0x238f00 PUSH	%RBP

0x238f01 MOV	%RSP,%RBP

0x238f04 PUSH	%R15

0x238f06 PUSH	%R14

0x238f08 PUSH	%RBX

0x238f09 SUB	$0x18,%RSP

0x238f0d MOV	%RDI,%R14

0x238f10 MOV	0x8(%RDI),%RDI

0x238f14 MOV	0x10(%R14),%RAX

0x238f18 CMP	%RAX,%RDI

0x238f1b JA	23914e

0x238f21 MOV	%RSI,%RBX

0x238f24 CMP	%RSI,%RAX

0x238f27 JAE	238f86

0x238f29 VMOVAPS	%XMM0,-0x30(%RBP)

0x238f2e TEST	%RAX,%RAX

0x238f31 JE	238f3c

0x238f33 MOV	0x18(%R14),%RDI

0x238f37 CALL	2f6600 <@plt_start@+0x30>

0x238f3c MOV	%RBX,%RAX

0x238f3f MOV	$0x1fffffffffffffff,%R15

0x238f49 SHR	$0x3c,%RAX

0x238f4d JNE	23913f

0x238f53 LEA	(,%RBX,8),%RDI

0x238f5b CALL	2f65e0 <@plt_start@+0x10>

0x238f60 LEA	(%RBX,%R15,1),%RDX

0x238f64 MOV	%RAX,0x18(%R14)

0x238f68 MOV	%RBX,0x8(%R14)

0x238f6c MOV	%RBX,0x10(%R14)

0x238f70 AND	%R15,%RDX

0x238f73 CMP	$0x3,%RDX

0x238f77 JAE	238fb8

0x238f79 VMOVAPS	-0x30(%RBP),%XMM1

0x238f7e MOV	%RAX,%RSI

0x238f81 JMP	2390f9

0x238f86 CMP	%RBX,%RDI

0x238f89 JAE	23912d

0x238f8f MOV	0x18(%R14),%RAX

0x238f93 LEA	(,%RBX,8),%RSI

0x238f9b LEA	(%RAX,%RDI,8),%RCX

0x238f9f SAL	$0x3,%RDI

0x238fa3 SUB	%RDI,%RSI

0x238fa6 ADD	$-0x8,%RSI

0x238faa CMP	$0x18,%RSI

0x238fae JAE	238fcb

0x238fb0 MOV	%RCX,%RDI

0x238fb3 JMP	239113

0x238fb8 VMOVAPS	-0x30(%RBP),%XMM1

0x238fbd LEA	0x1(%RDX),%RCX

0x238fc1 CMP	$0x1f,%RDX

0x238fc5 JAE	238fe9

0x238fc7 XOR	%EDX,%EDX

0x238fc9 JMP	23903a

0x238fcb MOV	%RSI,%RDX

0x238fce SHR	$0x3,%RDX

0x238fd2 INC	%RDX

0x238fd5 CMP	$0xf8,%RSI

0x238fdc JAE	23906c

0x238fe2 XOR	%ESI,%ESI

0x238fe4 JMP	2390c2

0x238fe9 VBROADCASTSD	%XMM1,%ZMM0

0x238fef MOV	%RCX,%RDX

0x238ff2 AND	$-0x20,%RDX

0x238ff6 XOR	%ESI,%ESI

0x238ff8 NOPL	(%RAX,%RAX,1)

(237) 0x239000 VMOVUPS	%ZMM0,(%RAX,%RSI,8)

(237) 0x239007 VMOVUPS	%ZMM0,0x40(%RAX,%RSI,8)

(237) 0x23900f VMOVUPS	%ZMM0,0x80(%RAX,%RSI,8)

(237) 0x239017 VMOVUPS	%ZMM0,0xc0(%RAX,%RSI,8)

(237) 0x23901f ADD	$0x20,%RSI

(237) 0x239023 CMP	%RSI,%RDX

(237) 0x239026 JNE	239000

0x239028 CMP	%RDX,%RCX

0x23902b JE	239131

0x239031 TEST	$0x1c,%CL

0x239034 JE	2390f5

0x23903a MOV	%RCX,%RDI

0x23903d AND	$-0x4,%RDI

0x239041 VBROADCASTSD	%XMM1,%YMM0

0x239046 LEA	(%RAX,%RDI,8),%RSI

0x23904a NOPW	(%RAX,%RAX,1)

(239) 0x239050 VMOVUPS	%YMM0,(%RAX,%RDX,8)

(239) 0x239055 ADD	$0x4,%RDX

(239) 0x239059 CMP	%RDX,%RDI

(239) 0x23905c JNE	239050

0x23905e CMP	%RDI,%RCX

0x239061 JNE	2390f9

0x239067 JMP	239131

0x23906c VBROADCASTSD	%XMM0,%ZMM1

0x239072 LEA	0xc0(%RDI,%RAX,1),%RDI

0x23907a MOV	%RDX,%RSI

0x23907d AND	$-0x20,%RSI

0x239081 XOR	%R8D,%R8D

0x239084 NOPW	%CS:(%RAX,%RAX,1)

(234) 0x239090 VMOVUPS	%ZMM1,-0xc0(%RDI,%R8,8)

(234) 0x239098 VMOVUPS	%ZMM1,-0x80(%RDI,%R8,8)

(234) 0x2390a0 VMOVUPS	%ZMM1,-0x40(%RDI,%R8,8)

(234) 0x2390a8 VMOVUPS	%ZMM1,(%RDI,%R8,8)

(234) 0x2390af ADD	$0x20,%R8

(234) 0x2390b3 CMP	%R8,%RSI

(234) 0x2390b6 JNE	239090

0x2390b8 CMP	%RSI,%RDX

0x2390bb JE	23912d

0x2390bd TEST	$0x1c,%DL

0x2390c0 JE	23910f

0x2390c2 MOV	%RDX,%R8

0x2390c5 AND	$-0x4,%R8

0x2390c9 VBROADCASTSD	%XMM0,%YMM1

0x2390ce LEA	(%RCX,%R8,8),%RDI

0x2390d2 NOPW	%CS:(%RAX,%RAX,1)

(236) 0x2390e0 VMOVUPS	%YMM1,(%RCX,%RSI,8)

(236) 0x2390e5 ADD	$0x4,%RSI

(236) 0x2390e9 CMP	%RSI,%R8

(236) 0x2390ec JNE	2390e0

0x2390ee CMP	%R8,%RDX

0x2390f1 JNE	239113

0x2390f3 JMP	23912d

0x2390f5 LEA	(%RAX,%RDX,8),%RSI

0x2390f9 LEA	(%RAX,%RBX,8),%RAX

0x2390fd NOPL	(%RAX)

(238) 0x239100 VMOVSD	%XMM1,(%RSI)

(238) 0x239104 ADD	$0x8,%RSI

(238) 0x239108 CMP	%RAX,%RSI

(238) 0x23910b JNE	239100

0x23910d JMP	239131

0x23910f LEA	(%RCX,%RSI,8),%RDI

0x239113 LEA	(%RAX,%RBX,8),%RAX

0x239117 NOPW	(%RAX,%RAX,1)

(235) 0x239120 VMOVSD	%XMM0,(%RDI)

(235) 0x239124 ADD	$0x8,%RDI

(235) 0x239128 CMP	%RAX,%RDI

(235) 0x23912b JNE	239120

0x23912d MOV	%RBX,0x8(%R14)

0x239131 ADD	$0x18,%RSP

0x239135 POP	%RBX

0x239136 POP	%R14

0x239138 POP	%R15

0x23913a POP	%RBP

0x23913b VZEROUPPER

0x23913e RET

0x23913f CMP	%R15,%RBX

0x239142 JBE	239149

0x239144 CALL	2f67d0 <@plt_start@+0x200>

0x239149 CALL	2f6950 <@plt_start@+0x380>

0x23914e MOV	$0x10,%EDI

0x239153 CALL	2f6800 <@plt_start@+0x230>

0x239158 MOV	%RAX,%RBX

0x23915b LEA	-0x30c23(%RIP),%RSI

0x239162 MOV	%RAX,%RDI

0x239165 CALL	2f6810 <@plt_start@+0x240>

0x23916a MOV	0xc30f7(%RIP),%RSI

0x239171 MOV	0xc30f8(%RIP),%RDX

0x239178 MOV	%RBX,%RDI

0x23917b CALL	2f6820 <@plt_start@+0x250>

0x239180 MOV	%RBX,%RDI

0x239183 MOV	%RAX,%R14

0x239186 CALL	2f6830 <@plt_start@+0x260>

0x23918b MOV	%R14,%RDI

0x23918e CALL	2f6620 <@plt_start@+0x50>

0x239193 INT	$0x3

0x239194 INT	$0x3

0x239195 INT	$0x3

0x239196 INT	$0x3

0x239197 INT	$0x3

0x239198 INT	$0x3

0x239199 INT	$0x3

0x23919a INT	$0x3

0x23919b INT	$0x3

0x23919c INT	$0x3

0x23919d INT	$0x3

0x23919e INT	$0x3

0x23919f INT	$0x3

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	OhmmsVector.h:182-302
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:111-117,127,145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:182-188,195-199,296-302
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923-924,1120

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.17 to 8.00 cycles (2.77x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 22.17 to 2.85 cycles (7.78x speedup).

Details

15% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

20% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
5% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

@plt_start@: 1 occurrences
unknown: 8 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	142
nb uops	133
loop length	538
used x86 registers	11
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	2
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.17 cycles
front end	22.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	16.50	14.50	14.25	14.25	16.50	7.67	7.67	7.67	0.00	2.00	2.00	0.00	0.50	0.50
cycles	16.50	14.50	14.25	14.25	16.50	7.67	7.67	7.67	0.00	2.00	2.00	0.00	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.17
Dispatch	16.50
Overall L1	22.17

Vectorization ratios

INT

all	5%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	42%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	15%
load	100%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	17%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	14%
load	25%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.17 cycles. At this rate:

3% of peak load performance is reached (3.61 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.17 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 22.17 to 16.50 cycles (1.34x speedup).

ASM code

In the binary file, the address of the function is: 238f00

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x8(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JA 23914e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x24e>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 238f86 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x86>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVAPS %XMM0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
TEST %RAX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 238f3c <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x3c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x18(%R14),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CALL 2f6600 <@plt_start@+0x30>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x1fffffffffffffff,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33
SHR $0x3c,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JNE 23913f <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x23f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
LEA (,%RBX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CALL 2f65e0 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
LEA (%RBX,%R15,1),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RAX,0x18(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RBX,0x8(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RBX,0x10(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
AND %R15,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x3,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 238fb8 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xb8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVAPS -0x30(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 2390f9 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1f9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
CMP %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 23912d <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x22d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x18(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (,%RBX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RAX,%RDI,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SAL $0x3,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB %RDI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $-0x8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 238fcb <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xcb>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 239113 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x213>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
VMOVAPS -0x30(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
LEA 0x1(%RDX),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x1f,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 238fe9 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xe9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 23903a <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x13a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0xf8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 23906c <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x16c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 2390c2 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1c2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
VBROADCASTSD %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x20,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 239131 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x231>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
TEST $0x1c,%CL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 2390f5 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1f5>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x4,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
LEA (%RAX,%RDI,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
CMP %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 2390f9 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1f9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
JMP 239131 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x231>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
VBROADCASTSD %XMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
LEA 0xc0(%RDI,%RAX,1),%RDI	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x20,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
CMP %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 23912d <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x22d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
TEST $0x1c,%DL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 23910f <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x20f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x4,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VBROADCASTSD %XMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
LEA (%RCX,%R8,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
CMP %R8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 239113 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x213>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
JMP 23912d <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x22d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
LEA (%RAX,%RDX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RAX,%RBX,8),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
JMP 239131 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x231>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
LEA (%RCX,%RSI,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RAX,%RBX,8),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV %RBX,0x8(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP %R15,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JBE 239149 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x249>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CALL 2f67d0 <@plt_start@+0x200>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
CALL 2f6950 <@plt_start@+0x380>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV $0x10,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CALL 2f6800 <@plt_start@+0x230>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x30c23(%RIP),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2f6810 <@plt_start@+0x240>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV 0xc30f7(%RIP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xc30f8(%RIP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2f6820 <@plt_start@+0x250>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2f6830 <@plt_start@+0x260>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2f6620 <@plt_start@+0x50>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3

Source file and lines	OhmmsVector.h:182-302
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:111-117,127,145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:182-188,195-199,296-302
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923-924,1120

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.17 to 8.00 cycles (2.77x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

15% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

20% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
5% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

@plt_start@: 1 occurrences
unknown: 8 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	142
nb uops	133
loop length	538
used x86 registers	11
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	2
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.17 cycles
front end	22.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	16.50	14.50	14.25	14.25	16.50	7.67	7.67	7.67	0.00	2.00	2.00	0.00	0.50	0.50
cycles	16.50	14.50	14.25	14.25	16.50	7.67	7.67	7.67	0.00	2.00	2.00	0.00	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.17
Dispatch	16.50
Overall L1	22.17

Vectorization ratios

INT

all	5%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	42%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	15%
load	100%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	17%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	14%
load	25%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.17 cycles. At this rate:

3% of peak load performance is reached (3.61 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.17 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 238f00

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x8(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x10(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JA 23914e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x24e>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 238f86 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x86>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVAPS %XMM0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
TEST %RAX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 238f3c <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x3c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x18(%R14),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CALL 2f6600 <@plt_start@+0x30>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x1fffffffffffffff,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33
SHR $0x3c,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
JNE 23913f <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x23f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
LEA (,%RBX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CALL 2f65e0 <@plt_start@+0x10>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
LEA (%RBX,%R15,1),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RAX,0x18(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RBX,0x8(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RBX,0x10(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
AND %R15,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x3,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 238fb8 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xb8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVAPS -0x30(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 2390f9 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1f9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
CMP %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 23912d <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x22d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x18(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (,%RBX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RAX,%RDI,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SAL $0x3,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB %RDI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $-0x8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 238fcb <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xcb>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 239113 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x213>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
VMOVAPS -0x30(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
LEA 0x1(%RDX),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x1f,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 238fe9 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xe9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 23903a <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x13a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
INC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0xf8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 23906c <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x16c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 2390c2 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1c2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
VBROADCASTSD %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x20,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 239131 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x231>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
TEST $0x1c,%CL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 2390f5 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1f5>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x4,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
LEA (%RAX,%RDI,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
CMP %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 2390f9 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1f9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
JMP 239131 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x231>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
VBROADCASTSD %XMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
LEA 0xc0(%RDI,%RAX,1),%RDI	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x20,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
CMP %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 23912d <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x22d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
TEST $0x1c,%DL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 23910f <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x20f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x4,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VBROADCASTSD %XMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
LEA (%RCX,%R8,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
CMP %R8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 239113 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x213>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
JMP 23912d <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x22d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
LEA (%RAX,%RDX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RAX,%RBX,8),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
JMP 239131 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x231>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
LEA (%RCX,%RSI,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RAX,%RBX,8),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV %RBX,0x8(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP %R15,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JBE 239149 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x249>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CALL 2f67d0 <@plt_start@+0x200>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
CALL 2f6950 <@plt_start@+0x380>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV $0x10,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CALL 2f6800 <@plt_start@+0x230>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x30c23(%RIP),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2f6810 <@plt_start@+0x240>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV 0xc30f7(%RIP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xc30f8(%RIP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2f6820 <@plt_start@+0x250>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2f6830 <@plt_start@+0x260>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 2f6620 <@plt_start@+0x50>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3

Name	Coverage (%)	Time (s)
▼_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd–	0.01	0.02
○Loop 237 - stl_algobase.h:924-924 - exec	0.01	0.01
○Loop 239 - stl_algobase.h:924-924 - exec	0	0
○Loop 235 - stl_algobase.h:923-924 - exec	0	0
○Loop 236 - stl_algobase.h:924-924 - exec	0	0
○Loop 234 - stl_algobase.h:924-924 - exec	0	0
○Loop 238 - stl_algobase.h:923-924 - exec	0	0

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CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code