OV - exec - Loop 929

	Loop Id: 929	Module: exec	Source: inner_product.hpp:155-155 [...]	Coverage: 0.31%

0x44ee10 MOVUPD	-0x58(%R10),%XMM5    [1]

0x44ee16 MOVUPD	-0x40(%R10),%XMM6    [1]

0x44ee1c MOVSD	-0x48(%R10),%XMM3    [1]

0x44ee22 MOVHPD	-0x30(%R10),%XMM3    [1]

0x44ee28 MOVUPD	-0x28(%R10),%XMM7    [1]

0x44ee2e MOVSD	-0x18(%R10),%XMM8    [1]

0x44ee34 MOVHPD	(%R10),%XMM8    [1]

0x44ee39 MOVUPD	-0x10(%R10),%XMM9    [1]

0x44ee3f MOVUPD	(%RSI,%R8,1),%XMM10    [2]

0x44ee45 MOVUPD	0x10(%RSI,%R8,1),%XMM2    [2]

0x44ee4c MULPD	%XMM2,%XMM8

0x44ee51 MULPD	%XMM10,%XMM3

0x44ee56 ADDPD	%XMM8,%XMM3

0x44ee5b MOVAPD	%XMM10,%XMM8

0x44ee60 UNPCKLPD	%XMM10,%XMM8

0x44ee65 MULPD	%XMM5,%XMM8

0x44ee6a ADDPD	%XMM4,%XMM8

0x44ee6f UNPCKHPD	%XMM10,%XMM10

0x44ee74 MULPD	%XMM6,%XMM10

0x44ee79 MOVAPD	%XMM2,%XMM4

0x44ee7d UNPCKLPD	%XMM2,%XMM4

0x44ee81 MULPD	%XMM7,%XMM4

0x44ee85 ADDPD	%XMM10,%XMM4

0x44ee8a ADDPD	%XMM8,%XMM4

0x44ee8f UNPCKHPD	%XMM2,%XMM2

0x44ee93 MULPD	%XMM9,%XMM2

0x44ee98 ADDPD	%XMM4,%XMM2

0x44ee9c MOVAPD	%XMM3,%XMM4

0x44eea0 UNPCKHPD	%XMM3,%XMM4

0x44eea4 ADDSD	%XMM3,%XMM4

0x44eea8 ADDSD	%XMM4,%XMM0

0x44eeac ADD	$0x20,%R8

0x44eeb0 ADD	$0x60,%R10

0x44eeb4 MOVAPD	%XMM2,%XMM4

0x44eeb8 CMP	%R8,%R15

0x44eebb JNE	44ee10

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 155 - 155

--------------------------------------------------------------------------------

155:   for (int i = 0; i < n; i++)

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 63 - 63

--------------------------------------------------------------------------------

63:     return (a * b);

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 157 - 157

--------------------------------------------------------------------------------

157:   if (UpdateMode == ORB_PBYP_RATIO)

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.89
CQA speedup if fully vectorized	5.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks
Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb
Source	inner_product.hpp:155-155,OperatorTags.h:63-63,DiracDeterminantRef.cpp:157-157
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	4.75
CQA cycles if fully vectorized	1.79
Front-end cycles	5.83
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	3.33
P5 cycles	3.33
P6 cycles	3.33
P7 cycles	3.00
P8 cycles	5.67
P9 cycles	5.83
P10 cycles	5.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	9
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	35.00
Nb loads	10.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.67
Nb FLOP add-sub	12.00
Nb FLOP mul	12.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.22
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	65.63
Vectorization ratio load	60.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	71.43
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	44.44
Vector-efficiency ratio all	20.70
Vector-efficiency ratio load	20.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	21.43
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.06

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.89
CQA speedup if fully vectorized	5.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks
Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb
Source	inner_product.hpp:155-155,OperatorTags.h:63-63,DiracDeterminantRef.cpp:157-157
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	4.75
CQA cycles if fully vectorized	1.79
Front-end cycles	5.83
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	3.33
P5 cycles	3.33
P6 cycles	3.33
P7 cycles	3.00
P8 cycles	5.67
P9 cycles	5.83
P10 cycles	5.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	9
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	35.00
Nb loads	10.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.67
Nb FLOP add-sub	12.00
Nb FLOP mul	12.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.22
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	65.63
Vectorization ratio load	60.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	71.43
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	44.44
Vector-efficiency ratio all	20.70
Vector-efficiency ratio load	20.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	21.43
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.06

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb
Source file and lines	inner_product.hpp:155-155
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:157

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 9.00 to 1.79 cycles (5.02x speedup).

Details

65% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX loads are used in vector version.
71% of SSE/AVX addition or subtraction instructions are used in vector version.
44% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 2 occurrences
MOVUPD: 6 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 11 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

12: addition or subtraction
12: multiply

The binary loop is loading 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	36
nb uops	35
loop length	177
used x86 registers	4
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.17

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.83 cycles
front end	5.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	3.33	3.33	3.33	3.00	5.67	5.83	5.50	0.00	0.00
cycles	0.75	0.75	0.50	0.50	0.50	3.33	3.33	3.33	3.00	5.67	5.83	5.50	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	9.00

Cycles summary

Front-end	5.83
Dispatch	5.83
Data deps.	9.00
Overall L1	9.00

Vectorization ratios

all	65%
load	60%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	44%

Vector efficiency ratios

all	20%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

14% of peak load performance is reached (14.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 44ee10

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	Latency	Recip. throughput
MOVUPD -0x58(%R10),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MOVUPD -0x40(%R10),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MOVSD -0x48(%R10),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MOVHPD -0x30(%R10),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	1	0.50
MOVUPD -0x28(%R10),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MOVSD -0x18(%R10),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MOVHPD (%R10),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	1	0.50
MOVUPD -0x10(%R10),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MOVUPD (%RSI,%R8,1),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MOVUPD 0x10(%RSI,%R8,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM2,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPD %XMM10,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM8,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
MOVAPD %XMM10,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKLPD %XMM10,%XMM8	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	1	0.40
MULPD %XMM5,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM4,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
UNPCKHPD %XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	1	0.40
MULPD %XMM6,%XMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKLPD %XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	1	0.40
MULPD %XMM7,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM10,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
ADDPD %XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
UNPCKHPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	1	0.40
MULPD %XMM9,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
MOVAPD %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKHPD %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	1	0.40
ADDSD %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
ADDSD %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
ADD $0x20,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x60,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVAPD %XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %R8,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 44ee10 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x300>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb
Source file and lines	inner_product.hpp:155-155
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:157

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

65% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX loads are used in vector version.
71% of SSE/AVX addition or subtraction instructions are used in vector version.
44% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 2 occurrences
MOVUPD: 6 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

12: addition or subtraction
12: multiply

The binary loop is loading 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	36
nb uops	35
loop length	177
used x86 registers	4
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.17

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.83 cycles
front end	5.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	3.33	3.33	3.33	3.00	5.67	5.83	5.50	0.00	0.00
cycles	0.75	0.75	0.50	0.50	0.50	3.33	3.33	3.33	3.00	5.67	5.83	5.50	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	9.00

Cycles summary

Front-end	5.83
Dispatch	5.83
Data deps.	9.00
Overall L1	9.00

Vectorization ratios

all	65%
load	60%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	44%

Vector efficiency ratios

all	20%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

14% of peak load performance is reached (14.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 44ee10

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	Latency	Recip. throughput
MOVUPD -0x58(%R10),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MOVUPD -0x40(%R10),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MOVSD -0x48(%R10),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MOVHPD -0x30(%R10),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	1	0.50
MOVUPD -0x28(%R10),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MOVSD -0x18(%R10),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MOVHPD (%R10),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	1	0.50
MOVUPD -0x10(%R10),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MOVUPD (%RSI,%R8,1),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MOVUPD 0x10(%RSI,%R8,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM2,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPD %XMM10,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM8,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
MOVAPD %XMM10,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKLPD %XMM10,%XMM8	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	1	0.40
MULPD %XMM5,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM4,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
UNPCKHPD %XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	1	0.40
MULPD %XMM6,%XMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKLPD %XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	1	0.40
MULPD %XMM7,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM10,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
ADDPD %XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
UNPCKHPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	1	0.40
MULPD %XMM9,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
MOVAPD %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKHPD %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	1	0.40
ADDSD %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
ADDSD %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
ADD $0x20,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x60,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVAPD %XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %R8,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 44ee10 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x300>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code