OV - exec - Loop 900

	Loop Id: 900	Module: exec	Source: inner_product.hpp:211-212	Coverage: 0.15%

0x44b3d0 MOVSD	(%R9),%XMM0    [3]

0x44b3d5 MOVSD	%XMM0,-0x38(%RBX)    [9]

0x44b3da LEA	(%R9,%RCX,8),%R12

0x44b3de MOVSD	(%R9,%RCX,8),%XMM0    [1]

0x44b3e4 MOVSD	%XMM0,-0x30(%RBX)    [9]

0x44b3e9 MOVSD	(%R8,%R12,1),%XMM0    [5]

0x44b3ef ADD	%R8,%R12

0x44b3f2 MOVSD	%XMM0,-0x28(%RBX)    [9]

0x44b3f7 MOVSD	(%R8,%R12,1),%XMM0    [8]

0x44b3fd ADD	%R8,%R12

0x44b400 MOVSD	%XMM0,-0x20(%RBX)    [9]

0x44b405 MOVSD	(%R8,%R12,1),%XMM0    [4]

0x44b40b ADD	%R8,%R12

0x44b40e MOVSD	%XMM0,-0x18(%RBX)    [9]

0x44b413 MOVSD	(%R8,%R12,1),%XMM0    [7]

0x44b419 ADD	%R8,%R12

0x44b41c MOVSD	%XMM0,-0x10(%RBX)    [9]

0x44b421 MOVSD	(%R8,%R12,1),%XMM0    [6]

0x44b427 ADD	%R8,%R12

0x44b42a MOVSD	%XMM0,-0x8(%RBX)    [9]

0x44b42f MOVSD	(%R8,%R12,1),%XMM0    [2]

0x44b435 MOVSD	%XMM0,(%RBX)    [9]

0x44b439 ADD	$0x40,%RBX

0x44b43d ADD	%R15,%R9

0x44b440 DEC	%RSI

0x44b443 JNE	44b3d0

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 211 - 212

--------------------------------------------------------------------------------

211:     for (size_t j = 0; j < m; ++j)

212:       B[i * ldb + j] = A[j * lda + i];

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.28
Bottlenecks	P5, P6, P7,
Function	_ZN11qmcplusplus11DiracMatrixIddE16invert_transposeERKNS_6MatrixIdSaIdEEERS4_RdS8_
Source	inner_product.hpp:211-212
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.33
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	1.00
Front-end cycles	4.17
DIV/SQRT cycles	2.25
P0 cycles	2.25
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	0.50
P4 cycles	5.33
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	25.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.28
Bottlenecks	P5, P6, P7,
Function	_ZN11qmcplusplus11DiracMatrixIddE16invert_transposeERKNS_6MatrixIdSaIdEEERS4_RdS8_
Source	inner_product.hpp:211-212
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.33
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	1.00
Front-end cycles	4.17
DIV/SQRT cycles	2.25
P0 cycles	2.25
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	0.50
P4 cycles	5.33
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	25.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN11qmcplusplus11DiracMatrixIddE16invert_transposeERKNS_6MatrixIdSaIdEEERS4_RdS8_
Source file and lines	inner_product.hpp:211-212
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:211-212.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.33 to 1.00 cycles (5.33x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.33 to 4.17 cycles (1.28x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	26
nb uops	25
loop length	117
used x86 registers	7
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.17 cycles
front end	4.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.25	2.25	2.00	2.00	0.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	4.00	4.00
cycles	2.25	2.25	2.00	2.00	0.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.17
Dispatch	5.33
Data deps.	1.00
Overall L1	5.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.33 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (12.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 44b3d0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
MOVSD (%R9),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOVSD %XMM0,-0x38(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
LEA (%R9,%RCX,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD (%R9,%RCX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOVSD %XMM0,-0x30(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD (%R8,%R12,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD %R8,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,-0x28(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD (%R8,%R12,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD %R8,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,-0x20(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD (%R8,%R12,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD %R8,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,-0x18(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD (%R8,%R12,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD %R8,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD (%R8,%R12,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD %R8,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD (%R8,%R12,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOVSD %XMM0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
ADD $0x40,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R15,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
DEC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 44b3d0 <_ZN11qmcplusplus11DiracMatrixIddE16invert_transposeERKNS_6MatrixIdSaIdEEERS4_RdS8_+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

Function	_ZN11qmcplusplus11DiracMatrixIddE16invert_transposeERKNS_6MatrixIdSaIdEEERS4_RdS8_
Source file and lines	inner_product.hpp:211-212
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.33 to 1.00 cycles (5.33x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.33 to 4.17 cycles (1.28x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	26
nb uops	25
loop length	117
used x86 registers	7
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.17 cycles
front end	4.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.25	2.25	2.00	2.00	0.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	4.00	4.00
cycles	2.25	2.25	2.00	2.00	0.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.17
Dispatch	5.33
Data deps.	1.00
Overall L1	5.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.33 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (12.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 44b3d0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
MOVSD (%R9),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOVSD %XMM0,-0x38(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
LEA (%R9,%RCX,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD (%R9,%RCX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOVSD %XMM0,-0x30(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD (%R8,%R12,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD %R8,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,-0x28(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD (%R8,%R12,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD %R8,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,-0x20(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD (%R8,%R12,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD %R8,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,-0x18(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD (%R8,%R12,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD %R8,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD (%R8,%R12,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD %R8,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD (%R8,%R12,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOVSD %XMM0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
ADD $0x40,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R15,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
DEC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 44b3d0 <_ZN11qmcplusplus11DiracMatrixIddE16invert_transposeERKNS_6MatrixIdSaIdEEERS4_RdS8_+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code