OV - exec - Loop 831

	Loop Id: 831	Module: exec	Source: inner_product.hpp:82-83 [...]	Coverage: 0.04%

0x4441d0 XORPD	%XMM0,%XMM0

0x4441d4 MOV	(%RBX),%RAX

0x4441d7 MOVSD	%XMM0,(%RAX,%R14,8)

0x4441dd INC	%R14

0x4441e0 CMP	%R14,0x260(%R12)

0x4441e8 JBE	44428c

0x4441ee MOV	(%R13),%RAX

0x4441f2 MOV	%R13,%RDI

0x4441f5 MOV	%R12,%RSI

0x4441f8 MOV	%R14D,%EDX

0x4441fb MOV	%R15,%RCX

0x4441fe CALLQ	0x10(%RAX)

0x444201 MOV	0x8(%R15),%RDX

0x444205 TEST	%EDX,%EDX

0x444207 JLE	4441d0

0x444209 MOV	0x18(%R15),%RAX

0x44420d MOV	-0x30(%RBP),%RCX

0x444211 MOV	0x18(%RCX),%RCX

0x444215 MOVSXD	%EDX,%RDX

0x444218 MOV	%RDX,%RSI

0x44421b AND	$-0x2,%RSI

0x44421f JE	444260

0x444221 XORPD	%XMM1,%XMM1

0x444225 XOR	%EDI,%EDI

0x444227 NOPW	(%RAX,%RAX,1)

  (833) 0x444230 MOVUPD	(%RCX,%RDI,8),%XMM0

  (833) 0x444235 MOVUPD	(%RAX,%RDI,8),%XMM2

  (833) 0x44423a MULPD	%XMM0,%XMM2

  (833) 0x44423e ADDPD	%XMM2,%XMM1

  (833) 0x444242 ADD	$0x2,%RDI

  (833) 0x444246 CMP	%RSI,%RDI

  (833) 0x444249 JL	444230

0x44424b MOVAPD	%XMM1,%XMM0

0x44424f UNPCKHPD	%XMM1,%XMM0

0x444253 ADDSD	%XMM1,%XMM0

0x444257 JMP	444270

0x444260 XORPD	%XMM0,%XMM0

0x444264 XOR	%ESI,%ESI

0x444266 JMP	444279

  (832) 0x444270 CMP	%RSI,%RDX

  (832) 0x444273 JE	4441d4

  (832) 0x444279 MOVSD	(%RCX,%RSI,8),%XMM1

  (832) 0x44427e MULSD	(%RAX,%RSI,8),%XMM1

  (832) 0x444283 ADDSD	%XMM1,%XMM0

  (832) 0x444287 INC	%RSI

  (832) 0x44428a JMP	444270

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 82 - 83

--------------------------------------------------------------------------------

82:   for (int i = 0; i < n; i++)

83:     res += a[i] * b[i];

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 178 - 249

--------------------------------------------------------------------------------

178:   inline size_t size() const { return nLocal; }

[...]

248:   inline pointer data() { return X; }

249:   inline const_pointer data() const { return X; }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1046

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h: 83 - 86

--------------------------------------------------------------------------------

83:     for (int iat = 0; iat < VP.getTotalNum(); ++iat)

84:     {

85:       evaluate(VP, iat, psi);

86:       ratios[iat] = simd::dot(psi.data(), psiinv.data(), psi.size());

Path /

Metric	Value
CQA speedup if no scalar integer	2.94
CQA speedup if FP arith vectorized	1.81
CQA speedup if fully vectorized	6.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.52
Bottlenecks
Function	_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E
Source	inner_product.hpp:82-83,OhmmsVector.h:178-178,OhmmsVector.h:248-249,stl_vector.h:1046-1046,SPOSet.h:83-86
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.92
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	2.17
CQA cycles if fully vectorized	0.63
Front-end cycles	3.92
DIV/SQRT cycles	2.00
P0 cycles	1.13
P1 cycles	1.13
P2 cycles	1.00
P3 cycles	2.00
P4 cycles	2.58
P5 cycles	2.58
P6 cycles	2.58
P7 cycles	0.00
P8 cycles	0.33
P9 cycles	0.42
P10 cycles	0.25
P11 cycles	0.25
P12 cycles	0.25
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.25
Nb uops	23.50
Nb loads	6.25
Nb stores	0.50
Nb stack references	0.75
FLOP/cycle	0.13
Nb FLOP add-sub	0.50
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.99
Bytes prefetched	0.00
Bytes loaded	50.00
Bytes stored	4.00
Stride 0	3.75
Stride 1	2.50
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.75
Vectorization ratio all	18.43
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.97
Vector-efficiency ratio all	14.23
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.49

Metric	Value
CQA speedup if no scalar integer	2.83
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.23
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E
Source	inner_product.hpp:82-83,OhmmsVector.h:178-178,OhmmsVector.h:248-249,stl_vector.h:1046-1046,SPOSet.h:83-86
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.83
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	2.83
CQA cycles if fully vectorized	0.54
Front-end cycles	2.83
DIV/SQRT cycles	1.50
P0 cycles	0.75
P1 cycles	0.75
P2 cycles	0.50
P3 cycles	1.50
P4 cycles	2.33
P5 cycles	2.33
P6 cycles	2.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	17.00
Nb loads	5.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.94
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	8.00
Stride 0	4.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	16.67
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.00
Vector-efficiency ratio all	14.58
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.00

Metric	Value
CQA speedup if no scalar integer	3.67
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.29
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.57
Bottlenecks	micro-operation queue,
Function	_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E
Source	inner_product.hpp:82-83,OhmmsVector.h:178-178,OhmmsVector.h:248-249,stl_vector.h:1046-1046,SPOSet.h:83-86
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.67
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	3.67
CQA cycles if fully vectorized	0.58
Front-end cycles	3.67
DIV/SQRT cycles	2.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	2.00
P4 cycles	2.33
P5 cycles	2.33
P6 cycles	2.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	22.00
Nb loads	6.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.09
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	0.00
Stride 0	3.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	16.67
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	16.67
Vector-efficiency ratio all	13.54
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.54

Metric	Value
CQA speedup if no scalar integer	2.78
CQA speedup if FP arith vectorized	4.97
CQA speedup if fully vectorized	7.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.79
Bottlenecks	micro-operation queue,
Function	_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E
Source	inner_product.hpp:82-83,OhmmsVector.h:178-178,OhmmsVector.h:248-249,stl_vector.h:1046-1046,SPOSet.h:83-86
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.17
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	0.84
CQA cycles if fully vectorized	0.58
Front-end cycles	4.17
DIV/SQRT cycles	2.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	2.00
P4 cycles	2.33
P5 cycles	2.33
P6 cycles	2.33
P7 cycles	0.00
P8 cycles	0.67
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.00
Nb uops	25.00
Nb loads	6.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.24
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.52
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	0.00
Stride 0	3.00
Stride 1	4.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	22.22
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	25.00
Vector-efficiency ratio all	14.58
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.84

Metric	Value
CQA speedup if no scalar integer	2.73
CQA speedup if FP arith vectorized	3.75
CQA speedup if fully vectorized	6.32
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	micro-operation queue,
Function	_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E
Source	inner_product.hpp:82-83,OhmmsVector.h:178-178,OhmmsVector.h:248-249,stl_vector.h:1046-1046,SPOSet.h:83-86
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	1.83
CQA cycles if FP arith vectorized	1.33
CQA cycles if fully vectorized	0.79
Front-end cycles	5.00
DIV/SQRT cycles	2.50
P0 cycles	1.75
P1 cycles	1.75
P2 cycles	1.50
P3 cycles	2.50
P4 cycles	3.33
P5 cycles	3.33
P6 cycles	3.33
P7 cycles	0.00
P8 cycles	0.67
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	30.00
Nb loads	8.00
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	0.20
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.40
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	8.00
Stride 0	5.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	18.18
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	22.22
Vector-efficiency ratio all	14.20
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.58

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E
Source file and lines	inner_product.hpp:82-83
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248-249
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:83-86

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.92 to 0.62 cycles (6.27x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences

Type of elements and instruction set

0 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 0.5 FP arithmetical operations:

0.50: addition or subtraction

The binary loop is loading 50 bytes (6 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	21.25
nb uops	23.50
loop length	75.50
used x86 registers	10.25
used mmx registers	0
used xmm registers	1.50
used ymm registers	0
used zmm registers	0
nb stack references	0.75

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	3.92 cycles
front end	3.92 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.00	1.13	1.13	1.00	2.00	2.58	2.58	2.58	0.00	0.33	0.42	0.25	0.25	0.25
cycles	2.00	1.13	1.13	1.00	2.00	2.58	2.58	2.58	0.00	0.33	0.42	0.25	0.25	0.25

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.92
Dispatch	2.58
Data deps.	1.00
Overall L1	3.92

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	60%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	83%

INT+FP

all	18%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	20%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

INT+FP

all	14%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.92 cycles. At this rate:

13% of peak load performance is reached (12.88 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.11 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E
Source file and lines	inner_product.hpp:82-83
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248-249
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:83-86

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.83 to 1.00 cycles (2.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	15
nb uops	17
loop length	57
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.83 cycles
front end	2.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.50	0.75	0.75	0.50	1.50	2.33	2.33	2.33	0.00	0.00	0.00	0.00	0.50	0.50
cycles	1.50	0.75	0.75	0.50	1.50	2.33	2.33	2.33	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.83
Dispatch	2.33
Data deps.	1.00
Overall L1	2.83

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	16%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	18%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	14%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.83 cycles. At this rate:

14% of peak load performance is reached (14.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.82 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.83 to 2.33 cycles (1.21x speedup).

ASM code

In the binary file, the address of the loop is: 4441ee

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
XORPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV (%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOVSD %XMM0,(%RAX,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
INC %R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP %R14,0x260(%R12)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JBE 44428c <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0xfc>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV (%R13),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALLQ 0x10(%RAX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	0	0	2.20
MOV 0x8(%R15),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
TEST %EDX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JLE 4441d0 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x40>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

Function	_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E
Source file and lines	inner_product.hpp:82-83
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248-249
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:83-86

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.67 to 1.00 cycles (3.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.67 to 0.58 cycles (6.29x speedup).

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 48 bytes.

General properties

nb instructions	19
nb uops	22
loop length	59
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.67 cycles
front end	3.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.00	1.00	1.00	1.00	2.00	2.33	2.33	2.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.00	1.00	1.00	1.00	2.00	2.33	2.33	2.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.67
Dispatch	2.33
Data deps.	1.00
Overall L1	3.67

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	16%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.67 cycles. At this rate:

13% of peak load performance is reached (13.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4441ee

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
MOV (%R13),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0.17
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0.17
MOV %R15,%RCX	1	0	0	0	0	0	0	0	0	0	0.17
CALLQ 0x10(%RAX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	2.20
MOV 0x8(%R15),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
TEST %EDX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 4441d0 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x40>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV 0x18(%R15),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x30(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x18(%RCX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.17
AND $-0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 444260 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0xd0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
XORPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.17
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25
JMP 444279 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0xe9>	1	0.50	0	0	0	0.50	0	0	0	0	1

Function	_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E
Source file and lines	inner_product.hpp:82-83
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248-249
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:83-86

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.17 to 1.50 cycles (2.78x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop is loading 48 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	23
nb uops	25
loop length	80
used x86 registers	10
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.17 cycles
front end	4.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.00	1.00	1.00	1.00	2.00	2.33	2.33	2.33	0.00	0.67	0.83	0.50	0.00	0.00
cycles	2.00	1.00	1.00	1.00	2.00	2.33	2.33	2.33	0.00	0.67	0.83	0.50	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.17
Dispatch	2.33
Data deps.	1.00
Overall L1	4.17

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	66%

INT+FP

all	22%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	18%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.17 cycles. At this rate:

12% of peak load performance is reached (11.52 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4441ee

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	FP3	Latency	Recip. throughput
MOV (%R13),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALLQ 0x10(%RAX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	0	0	0	2.20
MOV 0x8(%R15),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
TEST %EDX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JLE 4441d0 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x40>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1
MOV 0x18(%R15),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
MOV -0x30(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
MOV 0x18(%RCX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JE 444260 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0xd0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1
XORPD %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOVAPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKHPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	1	0.40
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
JMP 444270 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0xe0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1

Function	_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E
Source file and lines	inner_product.hpp:82-83
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248-249
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:83-86

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.00 to 1.83 cycles (2.73x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop is loading 64 bytes (8 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	28
nb uops	30
loop length	106
used x86 registers	11
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.50	1.75	1.75	1.50	2.50	3.33	3.33	3.33	0.00	0.67	0.83	0.50	0.50	0.50
cycles	2.50	1.75	1.75	1.50	2.50	3.33	3.33	3.33	0.00	0.67	0.83	0.50	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.00
Dispatch	3.33
Data deps.	1.00
Overall L1	5.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	40%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	66%

INT+FP

all	18%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	17%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	14%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

13% of peak load performance is reached (12.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.60 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4441ee

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV (%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	0.33
MOVSD %XMM0,(%RAX,%R14,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
INC %R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R14,0x260(%R12)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	1	0.33
JBE 44428c <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0xfc>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%R13),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	0.33
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALLQ 0x10(%RAX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	0	0	0	0	0	2.20
MOV 0x8(%R15),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	0.33
TEST %EDX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
JLE 4441d0 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x40>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x18(%R15),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	0.33
MOV -0x30(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	0.33
MOV 0x18(%RCX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	0.33
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
JE 444260 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0xd0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	0.50-1
XORPD %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOVAPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKHPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
JMP 444270 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0xe0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1

Report Configuration

Vectorization

Details

Workaround

CALL instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios