OV - exec - Loop 830

	Loop Id: 830	Module: exec	Source: MultiBsplineRef.hpp:242-262 [...]	Coverage: 6.71%

0x4438e0 MOVUPD	(%R12,%R13,8),%XMM11    [5]

0x4438e6 MOVUPD	(%RSI,%R13,8),%XMM1    [7]

0x4438ec MOVUPD	(%RAX,%R13,8),%XMM14    [14]

0x4438f2 MOVUPD	(%R11,%R13,8),%XMM2    [10]

0x4438f8 MOVAPD	%XMM11,%XMM9

0x4438fd MULPD	-0x3a0(%RBP),%XMM9    [15]

0x443906 MOVAPD	%XMM1,%XMM10

0x44390b MULPD	-0x390(%RBP),%XMM10    [15]

0x443914 ADDPD	%XMM9,%XMM10

0x443919 MOVAPD	%XMM14,%XMM8

0x44391e MULPD	-0x380(%RBP),%XMM8    [15]

0x443927 MOVAPD	-0x370(%RBP),%XMM9    [15]

0x443930 MULPD	%XMM2,%XMM9

0x443935 ADDPD	%XMM8,%XMM9

0x44393a ADDPD	%XMM10,%XMM9

0x44393f MOVAPD	%XMM11,%XMM8

0x443944 MULPD	-0x360(%RBP),%XMM8    [15]

0x44394d MOVAPD	%XMM1,%XMM0

0x443951 MULPD	-0x350(%RBP),%XMM0    [15]

0x443959 MOVAPD	%XMM14,%XMM5

0x44395e MULPD	-0x340(%RBP),%XMM5    [15]

0x443966 ADDPD	%XMM8,%XMM5

0x44396b MOVAPD	%XMM2,%XMM10

0x443970 MULPD	-0x240(%RBP),%XMM10    [15]

0x443979 ADDPD	%XMM0,%XMM10

0x44397e MULPD	%XMM4,%XMM10

0x443983 ADDPD	%XMM5,%XMM10

0x443988 MULPD	-0x330(%RBP),%XMM11    [15]

0x443991 MULPD	-0x320(%RBP),%XMM1    [15]

0x443999 ADDPD	%XMM11,%XMM1

0x44399e MULPD	-0x310(%RBP),%XMM14    [15]

0x4439a7 MULPD	%XMM4,%XMM2

0x4439ab ADDPD	%XMM14,%XMM2

0x4439b0 ADDPD	%XMM1,%XMM2

0x4439b4 MOVAPD	-0x3b0(%RBP),%XMM0    [15]

0x4439bc MULPD	%XMM9,%XMM0

0x4439c1 LEA	(%RBX,%R13,8),%R8

0x4439c5 MOVUPD	(%RBX,%R13,8),%XMM1    [3]

0x4439cb ADDPD	%XMM0,%XMM1

0x4439cf MOVUPD	%XMM1,(%RBX,%R13,8)    [3]

0x4439d5 MOVAPD	-0x150(%RBP),%XMM0    [15]

0x4439dd MULPD	%XMM9,%XMM0

0x4439e2 MOVUPD	(%R9,%R8,1),%XMM1    [4]

0x4439e8 ADDPD	%XMM0,%XMM1

0x4439ec MOVUPD	%XMM1,(%R9,%R8,1)    [4]

0x4439f2 LEA	(%R8,%R9,1),%R8

0x4439f6 MOVAPD	%XMM10,%XMM0

0x4439fb MULPD	%XMM3,%XMM0

0x4439ff MOVUPD	(%R9,%R8,1),%XMM1    [2]

0x443a05 ADDPD	%XMM0,%XMM1

0x443a09 MOVUPD	%XMM1,(%R9,%R8,1)    [2]

0x443a0f LEA	(%R8,%R9,1),%R8

0x443a13 MOVAPD	%XMM15,%XMM0

0x443a18 MULPD	%XMM9,%XMM0

0x443a1d MOVUPD	(%R9,%R8,1),%XMM1    [8]

0x443a23 ADDPD	%XMM0,%XMM1

0x443a27 MOVUPD	%XMM1,(%R9,%R8,1)    [8]

0x443a2d LEA	(%R8,%R9,1),%R8

0x443a31 MOVAPD	%XMM10,%XMM0

0x443a36 MULPD	%XMM13,%XMM0

0x443a3b MOVUPD	(%R9,%R8,1),%XMM1    [13]

0x443a41 ADDPD	%XMM0,%XMM1

0x443a45 MOVUPD	%XMM1,(%R9,%R8,1)    [13]

0x443a4b LEA	(%R8,%R9,1),%R8

0x443a4f MULPD	%XMM12,%XMM2

0x443a54 MOVUPD	(%R9,%R8,1),%XMM0    [6]

0x443a5a ADDPD	%XMM2,%XMM0

0x443a5e MOVUPD	%XMM0,(%R9,%R8,1)    [6]

0x443a64 MOVAPD	%XMM9,%XMM0

0x443a69 MULPD	%XMM3,%XMM0

0x443a6d MOVUPD	(%R15,%R13,8),%XMM1    [12]

0x443a73 ADDPD	%XMM0,%XMM1

0x443a77 MOVUPD	%XMM1,(%R15,%R13,8)    [12]

0x443a7d MOVAPD	%XMM9,%XMM0

0x443a82 MULPD	%XMM13,%XMM0

0x443a87 MOVUPD	(%RDX,%R13,8),%XMM1    [9]

0x443a8d ADDPD	%XMM0,%XMM1

0x443a91 MOVUPD	%XMM1,(%RDX,%R13,8)    [9]

0x443a97 MULPD	%XMM12,%XMM10

0x443a9c MOVUPD	(%RCX,%R13,8),%XMM0    [11]

0x443aa2 ADDPD	%XMM10,%XMM0

0x443aa7 MOVUPD	%XMM0,(%RCX,%R13,8)    [11]

0x443aad MULPD	%XMM12,%XMM9

0x443ab2 MOVUPD	(%R14,%R13,8),%XMM0    [1]

0x443ab8 ADDPD	%XMM9,%XMM0

0x443abd MOVUPD	%XMM0,(%R14,%R13,8)    [1]

0x443ac3 ADD	$0x2,%R13

0x443ac7 CMP	%RDI,%R13

0x443aca JL	4438e0

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 61 - 61

--------------------------------------------------------------------------------

61:     for (size_t d = 0; d < D; ++d)

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 242 - 262

--------------------------------------------------------------------------------

242:       for (int n = 0; n < iSplitPoint; n++)

243:       {

244:         T coefsv    = coefs[n];

245:         T coefsvzs  = coefszs[n];

246:         T coefsv2zs = coefs2zs[n];

247:         T coefsv3zs = coefs3zs[n];

248:

249:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

250:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

251:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

252:

253:         hxx[n] += pre20 * sum0;

254:         hxy[n] += pre11 * sum0;

255:         hxz[n] += pre10 * sum1;

256:         hyy[n] += pre02 * sum0;

257:         hyz[n] += pre01 * sum1;

258:         hzz[n] += pre00 * sum2;

259:         gx[n] += pre10 * sum0;

260:         gy[n] += pre01 * sum0;

261:         gz[n] += pre00 * sum1;

262:         vals[n] += pre00 * sum0;

Path /

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	1.19
CQA speedup if fully vectorized	2.55
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19
Bottlenecks	micro-operation queue,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source	TinyVector.h:61-61,MultiBsplineRef.hpp:242-262
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	14.67
CQA cycles if no scalar integer	13.83
CQA cycles if FP arith vectorized	12.33
CQA cycles if fully vectorized	5.75
Front-end cycles	14.67
DIV/SQRT cycles	1.75
P0 cycles	1.75
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	0.50
P4 cycles	12.33
P5 cycles	12.33
P6 cycles	12.33
P7 cycles	11.50
P8 cycles	11.50
P9 cycles	9.50
P10 cycles	9.50
P11 cycles	5.00
P12 cycles	5.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	89.00
Nb uops	88.00
Nb loads	27.00
Nb stores	10.00
Nb stack references	13.00
FLOP/cycle	5.73
Nb FLOP add-sub	38.00
Nb FLOP mul	46.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	40.36
Bytes prefetched	0.00
Bytes loaded	432.00
Bytes stored	160.00
Stride 0	1.00
Stride 1	9.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	1.19
CQA speedup if fully vectorized	2.55
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19
Bottlenecks	micro-operation queue,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source	TinyVector.h:61-61,MultiBsplineRef.hpp:242-262
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	14.67
CQA cycles if no scalar integer	13.83
CQA cycles if FP arith vectorized	12.33
CQA cycles if fully vectorized	5.75
Front-end cycles	14.67
DIV/SQRT cycles	1.75
P0 cycles	1.75
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	0.50
P4 cycles	12.33
P5 cycles	12.33
P6 cycles	12.33
P7 cycles	11.50
P8 cycles	11.50
P9 cycles	9.50
P10 cycles	9.50
P11 cycles	5.00
P12 cycles	5.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	89.00
Nb uops	88.00
Nb loads	27.00
Nb stores	10.00
Nb stack references	13.00
FLOP/cycle	5.73
Nb FLOP add-sub	38.00
Nb FLOP mul	46.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	40.36
Bytes prefetched	0.00
Bytes loaded	432.00
Bytes stored	160.00
Stride 0	1.00
Stride 1	9.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source file and lines	MultiBsplineRef.hpp:242-262
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:61
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:242-262

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.67 to 13.83 cycles (1.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 14.67 to 5.75 cycles (2.55x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 24 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 24 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

42 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 84 FP arithmetical operations:

38: addition or subtraction
46: multiply

The binary loop is loading 432 bytes (54 double precision FP elements). The binary loop is storing 160 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.

General properties

nb instructions	89
nb uops	88
loop length	496
used x86 registers	14
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	13
ADD-SUB / MUL ratio	0.83

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	14.67 cycles
front end	14.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.75	1.75	1.50	1.50	0.50	12.33	12.33	12.33	11.50	11.50	9.50	9.50	5.00	5.00
cycles	1.75	1.75	1.50	1.50	0.50	12.33	12.33	12.33	11.50	11.50	9.50	9.50	5.00	5.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	14.67
Dispatch	12.33
Data deps.	1.00
Overall L1	14.67

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.67 cycles. At this rate:

30% of peak load performance is reached (29.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (10.91 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.67 to 12.33 cycles (1.19x speedup).

ASM code

In the binary file, the address of the loop is: 4438e0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOVUPD (%R12,%R13,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD (%RSI,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD (%RAX,%R13,8),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD (%R11,%R13,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD %XMM11,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD -0x3a0(%RBP),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD -0x390(%RBP),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM14,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD -0x380(%RBP),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVAPD -0x370(%RBP),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM2,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM11,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD -0x360(%RBP),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD -0x350(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM14,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD -0x340(%RBP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM8,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM2,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD -0x240(%RBP),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPD %XMM4,%XMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM5,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPD -0x330(%RBP),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MULPD -0x320(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM11,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPD -0x310(%RBP),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD -0x3b0(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LEA (%RBX,%R13,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVUPD (%RBX,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM1,(%RBX,%R13,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD -0x150(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%R9,%R8,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM1,(%R9,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
LEA (%R8,%R9,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVAPD %XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%R9,%R8,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM1,(%R9,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
LEA (%R8,%R9,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVAPD %XMM15,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%R9,%R8,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM1,(%R9,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
LEA (%R8,%R9,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVAPD %XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%R9,%R8,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM1,(%R9,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
LEA (%R8,%R9,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MULPD %XMM12,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%R9,%R8,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM0,(%R9,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD %XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%R15,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM1,(%R15,%R13,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD %XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%RDX,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM1,(%RDX,%R13,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MULPD %XMM12,%XMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%RCX,%R13,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM0,(%RCX,%R13,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MULPD %XMM12,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%R14,%R13,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM0,(%R14,%R13,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
ADD $0x2,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RDI,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JL 4438e0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xd30>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source file and lines	MultiBsplineRef.hpp:242-262
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:61
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:242-262

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 14.67 to 5.75 cycles (2.55x speedup).

Details

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 24 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 24 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

42 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 84 FP arithmetical operations:

38: addition or subtraction
46: multiply

The binary loop is loading 432 bytes (54 double precision FP elements). The binary loop is storing 160 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.

General properties

nb instructions	89
nb uops	88
loop length	496
used x86 registers	14
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	13
ADD-SUB / MUL ratio	0.83

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	14.67 cycles
front end	14.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.75	1.75	1.50	1.50	0.50	12.33	12.33	12.33	11.50	11.50	9.50	9.50	5.00	5.00
cycles	1.75	1.75	1.50	1.50	0.50	12.33	12.33	12.33	11.50	11.50	9.50	9.50	5.00	5.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	14.67
Dispatch	12.33
Data deps.	1.00
Overall L1	14.67

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.67 cycles. At this rate:

30% of peak load performance is reached (29.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (10.91 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4438e0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOVUPD (%R12,%R13,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD (%RSI,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD (%RAX,%R13,8),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD (%R11,%R13,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD %XMM11,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD -0x3a0(%RBP),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD -0x390(%RBP),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM14,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD -0x380(%RBP),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVAPD -0x370(%RBP),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM2,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM11,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD -0x360(%RBP),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD -0x350(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM14,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD -0x340(%RBP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM8,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM2,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD -0x240(%RBP),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPD %XMM4,%XMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM5,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPD -0x330(%RBP),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MULPD -0x320(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM11,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPD -0x310(%RBP),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD -0x3b0(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LEA (%RBX,%R13,8),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVUPD (%RBX,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM1,(%RBX,%R13,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD -0x150(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%R9,%R8,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM1,(%R9,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
LEA (%R8,%R9,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVAPD %XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%R9,%R8,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM1,(%R9,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
LEA (%R8,%R9,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVAPD %XMM15,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%R9,%R8,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM1,(%R9,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
LEA (%R8,%R9,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVAPD %XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%R9,%R8,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM1,(%R9,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
LEA (%R8,%R9,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MULPD %XMM12,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%R9,%R8,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM0,(%R9,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD %XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%R15,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM1,(%R15,%R13,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD %XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%RDX,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM1,(%RDX,%R13,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MULPD %XMM12,%XMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%RCX,%R13,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM10,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM0,(%RCX,%R13,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MULPD %XMM12,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%R14,%R13,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM0,(%R14,%R13,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
ADD $0x2,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RDI,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JL 4438e0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xd30>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code