OV - exec - Loop 828

	Loop Id: 828	Module: exec	Source: MultiBsplineRef.hpp:227-262 [...]	Coverage: 0.02%

0x443760 MOV	-0xa8(%RBP),%R12

0x443767 LEA	0x1(%R12),%R8

0x44376c MOV	-0x98(%RBP),%RDI

0x443773 MOV	%R11,%R15

0x443776 MOV	-0x128(%RBP),%R11

0x44377d ADD	%RDI,%R11

0x443780 MOV	-0x130(%RBP),%R13

0x443787 ADD	%RDI,%R13

0x44378a ADD	%RDI,-0x118(%RBP)

0x443791 ADD	%RDI,-0x120(%RBP)

0x443798 ADD	%RDI,%R10

0x44379b ADD	%RDI,%R15

0x44379e MOV	%R15,-0xa0(%RBP)

0x4437a5 ADD	%RDI,%RAX

0x4437a8 ADD	%RDI,%RSI

0x4437ab CMP	$0x3,%R12

0x4437af MOV	%R8,-0xa8(%RBP)

0x4437b6 JE	443650

0x4437bc MOV	%R11,-0x128(%RBP)

0x4437c3 MOV	%R13,-0x130(%RBP)

0x4437ca CMPL	$0,-0x70(%RBP)

0x4437ce MOV	-0xa0(%RBP),%R11

0x4437d5 JLE	443760

0x4437d7 MOV	-0xa8(%RBP),%RDI

0x4437de MOVSD	-0x410(%RBP,%RDI,8),%XMM6

0x4437e7 MOVAPD	%XMM6,%XMM7

0x4437eb MULSD	-0x200(%RBP),%XMM7

0x4437f3 MOVAPD	%XMM6,%XMM3

0x4437f7 MOVSD	-0x1f8(%RBP),%XMM0

0x4437ff MULSD	%XMM0,%XMM3

0x443803 MOVSD	-0x1f0(%RBP),%XMM1

0x44380b MULSD	%XMM1,%XMM6

0x44380f MOVSD	-0x2a0(%RBP,%RDI,8),%XMM13

0x443819 MOVAPD	%XMM13,%XMM2

0x44381e MULSD	%XMM0,%XMM2

0x443822 MULSD	%XMM1,%XMM13

0x443827 MOVSD	-0x260(%RBP,%RDI,8),%XMM15

0x443831 MULSD	%XMM1,%XMM15

0x443836 MOV	-0x90(%RBP),%RDI

0x44383d TEST	%RDI,%RDI

0x443840 MOVAPD	%XMM3,-0x40(%RBP)

0x443845 JE	443b40

0x44384b MOV	%RAX,-0x208(%RBP)

0x443852 MOV	%RSI,-0x210(%RBP)

0x443859 MOVAPD	%XMM7,%XMM1

0x44385d UNPCKLPD	%XMM7,%XMM1

0x443861 MOVAPD	%XMM1,-0x3b0(%RBP)

0x443869 MOVAPD	%XMM2,-0x2f0(%RBP)

0x443871 UNPCKLPD	%XMM2,%XMM2

0x443875 MOVAPD	%XMM2,-0x150(%RBP)

0x44387d UNPCKLPD	%XMM3,%XMM3

0x443881 MOVAPD	-0x2d0(%RBP),%XMM4

0x443889 MOVAPD	%XMM15,-0x2e0(%RBP)

0x443892 UNPCKLPD	%XMM15,%XMM15

0x443897 MOVAPD	%XMM13,-0x300(%RBP)

0x4438a0 UNPCKLPD	%XMM13,%XMM13

0x4438a5 MOVAPD	%XMM6,%XMM12

0x4438aa UNPCKLPD	%XMM6,%XMM12

0x4438af XOR	%R13D,%R13D

0x4438b2 MOV	-0x50(%RBP),%R15

0x4438b6 MOV	-0x118(%RBP),%RSI

0x4438bd MOV	-0x120(%RBP),%R12

0x4438c4 MOV	-0x130(%RBP),%RAX

0x4438cb MOV	-0x128(%RBP),%R11

0x4438d2 NOPW	%CS:(%RAX,%RAX,1)

  (830) 0x4438e0 MOVUPD	(%R12,%R13,8),%XMM11

  (830) 0x4438e6 MOVUPD	(%RSI,%R13,8),%XMM1

  (830) 0x4438ec MOVUPD	(%RAX,%R13,8),%XMM14

  (830) 0x4438f2 MOVUPD	(%R11,%R13,8),%XMM2

  (830) 0x4438f8 MOVAPD	%XMM11,%XMM9

  (830) 0x4438fd MULPD	-0x3a0(%RBP),%XMM9

  (830) 0x443906 MOVAPD	%XMM1,%XMM10

  (830) 0x44390b MULPD	-0x390(%RBP),%XMM10

  (830) 0x443914 ADDPD	%XMM9,%XMM10

  (830) 0x443919 MOVAPD	%XMM14,%XMM8

  (830) 0x44391e MULPD	-0x380(%RBP),%XMM8

  (830) 0x443927 MOVAPD	-0x370(%RBP),%XMM9

  (830) 0x443930 MULPD	%XMM2,%XMM9

  (830) 0x443935 ADDPD	%XMM8,%XMM9

  (830) 0x44393a ADDPD	%XMM10,%XMM9

  (830) 0x44393f MOVAPD	%XMM11,%XMM8

  (830) 0x443944 MULPD	-0x360(%RBP),%XMM8

  (830) 0x44394d MOVAPD	%XMM1,%XMM0

  (830) 0x443951 MULPD	-0x350(%RBP),%XMM0

  (830) 0x443959 MOVAPD	%XMM14,%XMM5

  (830) 0x44395e MULPD	-0x340(%RBP),%XMM5

  (830) 0x443966 ADDPD	%XMM8,%XMM5

  (830) 0x44396b MOVAPD	%XMM2,%XMM10

  (830) 0x443970 MULPD	-0x240(%RBP),%XMM10

  (830) 0x443979 ADDPD	%XMM0,%XMM10

  (830) 0x44397e MULPD	%XMM4,%XMM10

  (830) 0x443983 ADDPD	%XMM5,%XMM10

  (830) 0x443988 MULPD	-0x330(%RBP),%XMM11

  (830) 0x443991 MULPD	-0x320(%RBP),%XMM1

  (830) 0x443999 ADDPD	%XMM11,%XMM1

  (830) 0x44399e MULPD	-0x310(%RBP),%XMM14

  (830) 0x4439a7 MULPD	%XMM4,%XMM2

  (830) 0x4439ab ADDPD	%XMM14,%XMM2

  (830) 0x4439b0 ADDPD	%XMM1,%XMM2

  (830) 0x4439b4 MOVAPD	-0x3b0(%RBP),%XMM0

  (830) 0x4439bc MULPD	%XMM9,%XMM0

  (830) 0x4439c1 LEA	(%RBX,%R13,8),%R8

  (830) 0x4439c5 MOVUPD	(%RBX,%R13,8),%XMM1

  (830) 0x4439cb ADDPD	%XMM0,%XMM1

  (830) 0x4439cf MOVUPD	%XMM1,(%RBX,%R13,8)

  (830) 0x4439d5 MOVAPD	-0x150(%RBP),%XMM0

  (830) 0x4439dd MULPD	%XMM9,%XMM0

  (830) 0x4439e2 MOVUPD	(%R9,%R8,1),%XMM1

  (830) 0x4439e8 ADDPD	%XMM0,%XMM1

  (830) 0x4439ec MOVUPD	%XMM1,(%R9,%R8,1)

  (830) 0x4439f2 LEA	(%R8,%R9,1),%R8

  (830) 0x4439f6 MOVAPD	%XMM10,%XMM0

  (830) 0x4439fb MULPD	%XMM3,%XMM0

  (830) 0x4439ff MOVUPD	(%R9,%R8,1),%XMM1

  (830) 0x443a05 ADDPD	%XMM0,%XMM1

  (830) 0x443a09 MOVUPD	%XMM1,(%R9,%R8,1)

  (830) 0x443a0f LEA	(%R8,%R9,1),%R8

  (830) 0x443a13 MOVAPD	%XMM15,%XMM0

  (830) 0x443a18 MULPD	%XMM9,%XMM0

  (830) 0x443a1d MOVUPD	(%R9,%R8,1),%XMM1

  (830) 0x443a23 ADDPD	%XMM0,%XMM1

  (830) 0x443a27 MOVUPD	%XMM1,(%R9,%R8,1)

  (830) 0x443a2d LEA	(%R8,%R9,1),%R8

  (830) 0x443a31 MOVAPD	%XMM10,%XMM0

  (830) 0x443a36 MULPD	%XMM13,%XMM0

  (830) 0x443a3b MOVUPD	(%R9,%R8,1),%XMM1

  (830) 0x443a41 ADDPD	%XMM0,%XMM1

  (830) 0x443a45 MOVUPD	%XMM1,(%R9,%R8,1)

  (830) 0x443a4b LEA	(%R8,%R9,1),%R8

  (830) 0x443a4f MULPD	%XMM12,%XMM2

  (830) 0x443a54 MOVUPD	(%R9,%R8,1),%XMM0

  (830) 0x443a5a ADDPD	%XMM2,%XMM0

  (830) 0x443a5e MOVUPD	%XMM0,(%R9,%R8,1)

  (830) 0x443a64 MOVAPD	%XMM9,%XMM0

  (830) 0x443a69 MULPD	%XMM3,%XMM0

  (830) 0x443a6d MOVUPD	(%R15,%R13,8),%XMM1

  (830) 0x443a73 ADDPD	%XMM0,%XMM1

  (830) 0x443a77 MOVUPD	%XMM1,(%R15,%R13,8)

  (830) 0x443a7d MOVAPD	%XMM9,%XMM0

  (830) 0x443a82 MULPD	%XMM13,%XMM0

  (830) 0x443a87 MOVUPD	(%RDX,%R13,8),%XMM1

  (830) 0x443a8d ADDPD	%XMM0,%XMM1

  (830) 0x443a91 MOVUPD	%XMM1,(%RDX,%R13,8)

  (830) 0x443a97 MULPD	%XMM12,%XMM10

  (830) 0x443a9c MOVUPD	(%RCX,%R13,8),%XMM0

  (830) 0x443aa2 ADDPD	%XMM10,%XMM0

  (830) 0x443aa7 MOVUPD	%XMM0,(%RCX,%R13,8)

  (830) 0x443aad MULPD	%XMM12,%XMM9

  (830) 0x443ab2 MOVUPD	(%R14,%R13,8),%XMM0

  (830) 0x443ab8 ADDPD	%XMM9,%XMM0

  (830) 0x443abd MOVUPD	%XMM0,(%R14,%R13,8)

  (830) 0x443ac3 ADD	$0x2,%R13

  (830) 0x443ac7 CMP	%RDI,%R13

  (830) 0x443aca JL	4438e0

0x443ad0 MOV	%RDI,%R13

0x443ad3 MOV	%RDI,%R8

0x443ad6 MOV	-0x70(%RBP),%RDI

0x443ada CMP	%RDI,%R8

0x443add MOVAPD	-0xd0(%RBP),%XMM12

0x443ae6 MOVAPD	-0x240(%RBP),%XMM5

0x443aee MOVAPD	-0x80(%RBP),%XMM9

0x443af4 MOVAPD	-0x60(%RBP),%XMM10

0x443afa MOVAPD	-0xc0(%RBP),%XMM11

0x443b03 MOV	-0x210(%RBP),%RSI

0x443b0a MOV	-0x208(%RBP),%RAX

0x443b11 MOV	-0xa0(%RBP),%R11

0x443b18 MOVAPD	-0x300(%RBP),%XMM13

0x443b21 MOVAPD	-0x2f0(%RBP),%XMM8

0x443b2a MOVAPD	-0x2e0(%RBP),%XMM4

0x443b32 JNE	443b60

0x443b34 JMP	443760

0x443b40 XOR	%R13D,%R13D

0x443b43 MOV	-0x70(%RBP),%RDI

0x443b47 MOV	-0x50(%RBP),%R15

0x443b4b MOVAPD	%XMM2,%XMM8

0x443b50 MOVAPD	%XMM15,%XMM4

0x443b55 NOPW	%CS:(%RAX,%RAX,1)

  (829) 0x443b60 MOVAPD	%XMM6,%XMM15

  (829) 0x443b65 MOVAPD	%XMM8,%XMM14

  (829) 0x443b6a MOVSD	(%RSI,%R13,8),%XMM8

  (829) 0x443b70 MOVSD	(%RAX,%R13,8),%XMM2

  (829) 0x443b76 MOVSD	(%R11,%R13,8),%XMM0

  (829) 0x443b7c MOVSD	(%R10,%R13,8),%XMM3

  (829) 0x443b82 MOVAPD	%XMM4,%XMM6

  (829) 0x443b86 MOVAPD	%XMM13,%XMM4

  (829) 0x443b8b MOVAPD	%XMM7,%XMM13

  (829) 0x443b90 MOVAPD	%XMM12,%XMM7

  (829) 0x443b95 MOVAPD	%XMM5,%XMM12

  (829) 0x443b9a MOVAPD	%XMM8,%XMM5

  (829) 0x443b9f UNPCKLPD	%XMM2,%XMM5

  (829) 0x443ba3 MOVAPD	%XMM0,%XMM1

  (829) 0x443ba7 UNPCKLPD	%XMM9,%XMM1

  (829) 0x443bac MOVAPD	-0x160(%RBP),%XMM9

  (829) 0x443bb5 UNPCKLPD	%XMM3,%XMM9

  (829) 0x443bba MULPD	%XMM1,%XMM9

  (829) 0x443bbf MULPD	%XMM10,%XMM5

  (829) 0x443bc4 ADDPD	%XMM9,%XMM5

  (829) 0x443bc9 MOVAPD	%XMM5,%XMM1

  (829) 0x443bcd UNPCKHPD	%XMM5,%XMM1

  (829) 0x443bd1 ADDSD	%XMM5,%XMM1

  (829) 0x443bd5 MOVAPD	%XMM8,%XMM5

  (829) 0x443bda MULSD	%XMM11,%XMM5

  (829) 0x443bdf MOVAPD	%XMM2,%XMM10

  (829) 0x443be4 MULSD	-0xe0(%RBP),%XMM10

  (829) 0x443bed MOVAPD	%XMM0,%XMM11

  (829) 0x443bf2 MULSD	-0x3f0(%RBP),%XMM11

  (829) 0x443bfb ADDSD	%XMM5,%XMM11

  (829) 0x443c00 MOVAPD	%XMM12,%XMM5

  (829) 0x443c05 MOVAPD	%XMM7,%XMM12

  (829) 0x443c0a MOVAPD	%XMM13,%XMM7

  (829) 0x443c0f MOVAPD	%XMM4,%XMM13

  (829) 0x443c14 MOVAPD	%XMM6,%XMM4

  (829) 0x443c18 MOVAPD	%XMM3,%XMM9

  (829) 0x443c1d MULSD	%XMM5,%XMM9

  (829) 0x443c22 ADDSD	%XMM10,%XMM9

  (829) 0x443c27 MOVAPD	-0x60(%RBP),%XMM10

  (829) 0x443c2d MULSD	%XMM12,%XMM9

  (829) 0x443c32 ADDSD	%XMM11,%XMM9

  (829) 0x443c37 MOVAPD	-0xc0(%RBP),%XMM11

  (829) 0x443c40 MULSD	-0x3e0(%RBP),%XMM8

  (829) 0x443c49 MULSD	-0x3d0(%RBP),%XMM2

  (829) 0x443c51 ADDSD	%XMM8,%XMM2

  (829) 0x443c56 MOVAPD	%XMM14,%XMM8

  (829) 0x443c5b MOVAPD	%XMM15,%XMM6

  (829) 0x443c60 MOVAPD	-0x40(%RBP),%XMM14

  (829) 0x443c66 MULSD	-0x3c0(%RBP),%XMM0

  (829) 0x443c6e MULSD	%XMM12,%XMM3

  (829) 0x443c73 ADDSD	%XMM0,%XMM3

  (829) 0x443c77 MOVAPD	%XMM7,%XMM0

  (829) 0x443c7b MULSD	%XMM1,%XMM0

  (829) 0x443c7f ADDSD	(%RBX,%R13,8),%XMM0

  (829) 0x443c85 LEA	(%RBX,%R13,8),%R8

  (829) 0x443c89 MOVSD	%XMM0,(%RBX,%R13,8)

  (829) 0x443c8f MOVAPD	%XMM8,%XMM0

  (829) 0x443c94 MULSD	%XMM1,%XMM0

  (829) 0x443c98 ADDSD	(%R9,%R8,1),%XMM0

  (829) 0x443c9e MOVSD	%XMM0,(%R9,%R8,1)

  (829) 0x443ca4 LEA	(%R8,%R9,1),%R8

  (829) 0x443ca8 MOVAPD	%XMM9,%XMM0

  (829) 0x443cad MULSD	%XMM14,%XMM0

  (829) 0x443cb2 ADDSD	(%R9,%R8,1),%XMM0

  (829) 0x443cb8 MOVSD	%XMM0,(%R9,%R8,1)

  (829) 0x443cbe LEA	(%R8,%R9,1),%R8

  (829) 0x443cc2 MOVAPD	%XMM4,%XMM0

  (829) 0x443cc6 MULSD	%XMM1,%XMM0

  (829) 0x443cca ADDSD	(%R9,%R8,1),%XMM0

  (829) 0x443cd0 MOVSD	%XMM0,(%R9,%R8,1)

  (829) 0x443cd6 LEA	(%R8,%R9,1),%R8

  (829) 0x443cda MOVAPD	%XMM9,%XMM0

  (829) 0x443cdf MULSD	%XMM13,%XMM0

  (829) 0x443ce4 ADDSD	(%R9,%R8,1),%XMM0

  (829) 0x443cea ADDSD	%XMM2,%XMM3

  (829) 0x443cee MOVSD	%XMM0,(%R9,%R8,1)

  (829) 0x443cf4 LEA	(%R8,%R9,1),%R8

  (829) 0x443cf8 MULSD	%XMM15,%XMM3

  (829) 0x443cfd ADDSD	(%R9,%R8,1),%XMM3

  (829) 0x443d03 MOVSD	%XMM3,(%R9,%R8,1)

  (829) 0x443d09 MOVAPD	%XMM1,%XMM0

  (829) 0x443d0d MULSD	%XMM14,%XMM0

  (829) 0x443d12 ADDSD	(%R15,%R13,8),%XMM0

  (829) 0x443d18 MOVSD	%XMM0,(%R15,%R13,8)

  (829) 0x443d1e MOVAPD	%XMM1,%XMM0

  (829) 0x443d22 MULSD	%XMM13,%XMM0

  (829) 0x443d27 ADDSD	(%RDX,%R13,8),%XMM0

  (829) 0x443d2d MOVSD	%XMM0,(%RDX,%R13,8)

  (829) 0x443d33 MULSD	%XMM15,%XMM9

  (829) 0x443d38 ADDSD	(%RCX,%R13,8),%XMM9

  (829) 0x443d3e MOVSD	%XMM9,(%RCX,%R13,8)

  (829) 0x443d44 MOVAPD	-0x80(%RBP),%XMM9

  (829) 0x443d4a MULSD	%XMM15,%XMM1

  (829) 0x443d4f ADDSD	(%R14,%R13,8),%XMM1

  (829) 0x443d55 MOVSD	%XMM1,(%R14,%R13,8)

  (829) 0x443d5b INC	%R13

  (829) 0x443d5e CMP	%R13,%RDI

  (829) 0x443d61 JNE	443b60

0x443d67 JMP	443760

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 61 - 61

--------------------------------------------------------------------------------

61:     for (size_t d = 0; d < D; ++d)

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 227 - 262

--------------------------------------------------------------------------------

227:     for (int j = 0; j < 4; j++)

[...]

234:       const T pre20 = d2a[i] * b[j];

235:       const T pre10 = da[i] * b[j];

236:       const T pre00 = a[i] * b[j];

237:       const T pre11 = da[i] * db[j];

238:       const T pre01 = a[i] * db[j];

239:       const T pre02 = a[i] * d2b[j];

240:

241:       const int iSplitPoint = num_splines;

242:       for (int n = 0; n < iSplitPoint; n++)

243:       {

244:         T coefsv    = coefs[n];

245:         T coefsvzs  = coefszs[n];

246:         T coefsv2zs = coefs2zs[n];

247:         T coefsv3zs = coefs3zs[n];

248:

249:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

250:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

251:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

252:

253:         hxx[n] += pre20 * sum0;

254:         hxy[n] += pre11 * sum0;

255:         hxz[n] += pre10 * sum1;

256:         hyy[n] += pre02 * sum0;

257:         hyz[n] += pre01 * sum1;

258:         hzz[n] += pre00 * sum2;

259:         gx[n] += pre10 * sum0;

260:         gy[n] += pre01 * sum0;

261:         gz[n] += pre00 * sum1;

262:         vals[n] += pre00 * sum0;

Path /

Metric	Value
CQA speedup if no scalar integer	1.73
CQA speedup if FP arith vectorized	1.16
CQA speedup if fully vectorized	4.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source	TinyVector.h:61-61,MultiBsplineRef.hpp:227-227,MultiBsplineRef.hpp:234-239,MultiBsplineRef.hpp:242-242,MultiBsplineRef.hpp:253-258
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.79
CQA cycles if no scalar integer	6.25
CQA cycles if FP arith vectorized	9.31
CQA cycles if fully vectorized	2.69
Front-end cycles	10.04
DIV/SQRT cycles	3.63
P0 cycles	3.63
P1 cycles	3.50
P2 cycles	3.50
P3 cycles	2.00
P4 cycles	10.58
P5 cycles	10.58
P6 cycles	10.58
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	1.50
P10 cycles	1.50
P11 cycles	1.63
P12 cycles	1.63
P13 cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	60.25
Nb loads	23.50
Nb stores	10.25
Nb stack references	19.00
FLOP/cycle	0.42
Nb FLOP add-sub	0.00
Nb FLOP mul	4.50
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.90
Bytes prefetched	0.00
Bytes loaded	220.00
Bytes stored	108.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	7.75
Stride indirect	0.75
Vectorization ratio all	19.79
Vectorization ratio load	17.31
Vectorization ratio store	25.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	28.59
Vector-efficiency ratio all	14.79
Vector-efficiency ratio load	14.42
Vector-efficiency ratio store	15.63
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.36

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.88
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	micro-operation queue,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source	TinyVector.h:61-61,MultiBsplineRef.hpp:227-227,MultiBsplineRef.hpp:234-239,MultiBsplineRef.hpp:242-242,MultiBsplineRef.hpp:253-258
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.17
CQA cycles if no scalar integer	4.17
CQA cycles if FP arith vectorized	4.17
CQA cycles if fully vectorized	0.71
Front-end cycles	4.17
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	1.00
P4 cycles	4.00
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.00
Nb uops	25.00
Nb loads	8.00
Nb stores	6.00
Nb stack references	8.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.92
Bytes prefetched	0.00
Bytes loaded	60.00
Bytes stored	48.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	2.00
CQA speedup if FP arith vectorized	1.30
CQA speedup if fully vectorized	5.13
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	micro-operation queue,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source	TinyVector.h:61-61,MultiBsplineRef.hpp:227-227,MultiBsplineRef.hpp:234-239,MultiBsplineRef.hpp:242-242,MultiBsplineRef.hpp:253-258
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.33
CQA cycles if no scalar integer	4.17
CQA cycles if FP arith vectorized	6.42
CQA cycles if fully vectorized	1.63
Front-end cycles	8.33
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	3.50
P3 cycles	2.00
P4 cycles	7.67
P5 cycles	7.67
P6 cycles	7.67
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	50.00
Nb loads	18.00
Nb stores	7.00
Nb stack references	14.00
FLOP/cycle	0.72
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.48
Bytes prefetched	0.00
Bytes loaded	140.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	10.00
Stride indirect	1.00
Vectorization ratio all	16.67
Vectorization ratio load	0.00
Vectorization ratio store	14.29
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	55.56
Vector-efficiency ratio all	14.24
Vector-efficiency ratio load	12.02
Vector-efficiency ratio store	14.29
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.06

Metric	Value
CQA speedup if no scalar integer	1.84
CQA speedup if FP arith vectorized	1.15
CQA speedup if fully vectorized	3.64
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source	TinyVector.h:61-61,MultiBsplineRef.hpp:227-227,MultiBsplineRef.hpp:234-239,MultiBsplineRef.hpp:242-242,MultiBsplineRef.hpp:253-258
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.33
CQA cycles if no scalar integer	8.33
CQA cycles if FP arith vectorized	13.33
CQA cycles if fully vectorized	4.21
Front-end cycles	13.83
DIV/SQRT cycles	4.00
P0 cycles	4.00
P1 cycles	3.75
P2 cycles	3.75
P3 cycles	2.50
P4 cycles	15.33
P5 cycles	15.33
P6 cycles	15.33
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	82.00
Nb uops	83.00
Nb loads	34.00
Nb stores	14.00
Nb stack references	27.00
FLOP/cycle	0.39
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.61
Bytes prefetched	0.00
Bytes loaded	340.00
Bytes stored	160.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	10.00
Stride indirect	1.00
Vectorization ratio all	31.25
Vectorization ratio load	34.62
Vectorization ratio store	42.86
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	29.41
Vector-efficiency ratio all	16.21
Vector-efficiency ratio load	16.59
Vector-efficiency ratio store	17.86
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.44

Metric	Value
CQA speedup if no scalar integer	1.84
CQA speedup if FP arith vectorized	1.15
CQA speedup if fully vectorized	3.64
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source	TinyVector.h:61-61,MultiBsplineRef.hpp:227-227,MultiBsplineRef.hpp:234-239,MultiBsplineRef.hpp:242-242,MultiBsplineRef.hpp:253-258
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.33
CQA cycles if no scalar integer	8.33
CQA cycles if FP arith vectorized	13.33
CQA cycles if fully vectorized	4.21
Front-end cycles	13.83
DIV/SQRT cycles	4.00
P0 cycles	4.00
P1 cycles	3.75
P2 cycles	3.75
P3 cycles	2.50
P4 cycles	15.33
P5 cycles	15.33
P6 cycles	15.33
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	82.00
Nb uops	83.00
Nb loads	34.00
Nb stores	14.00
Nb stack references	27.00
FLOP/cycle	0.39
Nb FLOP add-sub	0.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.61
Bytes prefetched	0.00
Bytes loaded	340.00
Bytes stored	160.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	11.00
Stride indirect	1.00
Vectorization ratio all	31.25
Vectorization ratio load	34.62
Vectorization ratio store	42.86
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	29.41
Vector-efficiency ratio all	16.21
Vector-efficiency ratio load	16.59
Vector-efficiency ratio store	17.86
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.44

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source file and lines	MultiBsplineRef.hpp:227-262
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:61
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:227,234-262

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 10.79 to 2.69 cycles (4.02x speedup).

Details

19% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

17% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
28% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 2 occurrences

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 4.5 FP arithmetical operations:

4.50: multiply

The binary loop is loading 220 bytes (27 double precision FP elements). The binary loop is storing 108 bytes (13 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	59
nb uops	60.25
loop length	342.25
used x86 registers	10
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	19

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	10.04 cycles
front end	10.04 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.63	3.63	3.50	3.50	2.00	10.58	10.58	10.58	2.25	2.25	1.50	1.50	1.63	1.63
cycles	3.63	3.63	3.50	3.50	2.00	10.58	10.58	10.58	2.25	2.25	1.50	1.50	1.63	1.63

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	10.04
Dispatch	10.58
Data deps.	0.00
Overall L1	10.79

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	47%
load	40%
store	100%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	63%

INT+FP

all	19%
load	17%
store	25%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Vector efficiency ratios

INT

all	12%
load	11%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	18%
load	17%
store	25%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	14%
load	14%
store	15%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.79 cycles. At this rate:

19% of peak load performance is reached (18.89 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (10.02 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source file and lines	MultiBsplineRef.hpp:227-262
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:61
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:227,234-262

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.17 to 0.71 cycles (5.88x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 60 bytes. The binary loop is storing 48 bytes.

General properties

nb instructions	23
nb uops	25
loop length	119
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.17 cycles
front end	4.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.00	3.00	3.00	3.00	1.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.00	3.00	3.00	3.00	1.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	4.17
Dispatch	4.00
Data deps.	0.00
Overall L1	4.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.17 cycles. At this rate:

14% of peak load performance is reached (14.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (11.52 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 4437bc

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
MOV -0xa8(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
LEA 0x1(%R12),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x98(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R11,%R15	1	0	0	0	0	0	0	0	0	0	0.17
MOV -0x128(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
ADD %RDI,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x130(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
ADD %RDI,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %RDI,-0x118(%RBP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.50
ADD %RDI,-0x120(%RBP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.50
ADD %RDI,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %RDI,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R15,-0xa0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %RDI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP $0x3,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R8,-0xa8(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
JE 443650 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xaa0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV %R11,-0x128(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %R13,-0x130(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
CMPL $0,-0x70(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV -0xa0(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
JLE 443760 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xbb0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source file and lines	MultiBsplineRef.hpp:227-262
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:61
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:227,234-262

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.33 to 4.17 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

16% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
14% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
55% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 2 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 10 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

6: multiply

The binary loop is loading 140 bytes (17 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	49
nb uops	50
loop length	272
used x86 registers	10
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.33 cycles
front end	8.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.50	3.50	3.50	3.50	2.00	7.67	7.67	7.67	3.00	3.00	0.00	0.00	0.50	0.50
cycles	3.50	3.50	3.50	3.50	2.00	7.67	7.67	7.67	3.00	3.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	8.33
Dispatch	7.67
Data deps.	0.00
Overall L1	8.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	35%
load	0%
store	100%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	16%
load	0%
store	14%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	55%

Vector efficiency ratios

INT

all	11%
load	11%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	16%
load	12%
store	25%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	14%
load	12%
store	14%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.33 cycles. At this rate:

17% of peak load performance is reached (16.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (7.68 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.33 to 7.67 cycles (1.09x speedup).

ASM code

In the binary file, the address of the loop is: 4437bc

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
MOV -0xa8(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
LEA 0x1(%R12),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV -0x98(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %R11,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x128(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
ADD %RDI,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV -0x130(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
ADD %RDI,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD %RDI,-0x118(%RBP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADD %RDI,-0x120(%RBP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADD %RDI,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD %RDI,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R15,-0xa0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD %RDI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $0x3,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R8,-0xa8(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
JE 443650 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xaa0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %R11,-0x128(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV %R13,-0x130(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
CMPL $0,-0x70(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
MOV -0xa0(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
JLE 443760 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xbb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV -0xa8(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOVSD -0x410(%RBP,%RDI,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MOVAPD %XMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULSD -0x200(%RBP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
MOVAPD %XMM6,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVSD -0x1f8(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MULSD %XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVSD -0x1f0(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MULSD %XMM1,%XMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVSD -0x2a0(%RBP,%RDI,8),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MOVAPD %XMM13,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULSD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULSD %XMM1,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVSD -0x260(%RBP,%RDI,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MULSD %XMM1,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOV -0x90(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
TEST %RDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVAPD %XMM3,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
JE 443b40 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xf90>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV -0x70(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV -0x50(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOVAPD %XMM2,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVAPD %XMM15,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
JMP 443760 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xbb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source file and lines	MultiBsplineRef.hpp:227-262
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:61
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:227,234-262

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.33 to 8.33 cycles (1.84x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 15.33 to 4.21 cycles (3.64x speedup).

Details

31% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

34% of SSE/AVX loads are used in vector version.
42% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
29% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 15.33 to 13.83 cycles (1.11x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 2 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 10 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

6: multiply

The binary loop is loading 340 bytes (42 double precision FP elements). The binary loop is storing 160 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	82
nb uops	83
loop length	489
used x86 registers	10
used mmx registers	0
used xmm registers	15
used ymm registers	0
used zmm registers	0
nb stack references	27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.83 cycles
front end	13.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.00	4.00	3.75	3.75	2.50	15.33	15.33	15.33	3.00	3.00	3.00	3.00	3.00	3.00
cycles	4.00	4.00	3.75	3.75	2.50	15.33	15.33	15.33	3.00	3.00	3.00	3.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	13.83
Dispatch	15.33
Data deps.	0.00
Overall L1	15.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	54%
load	60%
store	100%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

INT+FP

all	31%
load	34%
store	42%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	29%

Vector efficiency ratios

INT

all	12%
load	11%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	19%
load	20%
store	25%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	16%
load	16%
store	17%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.33 cycles. At this rate:

23% of peak load performance is reached (22.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (10.43 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4437bc

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV -0xa8(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA 0x1(%R12),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x98(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R11,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x128(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %RDI,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x130(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %RDI,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RDI,-0x118(%RBP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD %RDI,-0x120(%RBP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD %RDI,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RDI,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R15,-0xa0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RDI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x3,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R8,-0xa8(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JE 443650 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xaa0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R11,-0x128(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %R13,-0x130(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
CMPL $0,-0x70(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV -0xa0(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JLE 443760 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xbb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV -0xa8(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSD -0x410(%RBP,%RDI,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVAPD %XMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULSD -0x200(%RBP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM6,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVSD -0x1f8(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MULSD %XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVSD -0x1f0(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MULSD %XMM1,%XMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVSD -0x2a0(%RBP,%RDI,8),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVAPD %XMM13,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULSD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULSD %XMM1,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVSD -0x260(%RBP,%RDI,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MULSD %XMM1,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOV -0x90(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
TEST %RDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVAPD %XMM3,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
JE 443b40 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xf90>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RAX,-0x208(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RSI,-0x210(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVAPD %XMM7,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKLPD %XMM7,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVAPD %XMM1,-0x3b0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD %XMM2,-0x2f0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
UNPCKLPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVAPD %XMM2,-0x150(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
UNPCKLPD %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVAPD -0x2d0(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD %XMM15,-0x2e0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
UNPCKLPD %XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVAPD %XMM13,-0x300(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
UNPCKLPD %XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVAPD %XMM6,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKLPD %XMM6,%XMM12	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV -0x50(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x118(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x120(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x130(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x128(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x70(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP %RDI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVAPD -0xd0(%RBP),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0x240(%RBP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0x80(%RBP),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0x60(%RBP),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0xc0(%RBP),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOV -0x210(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x208(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0xa0(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVAPD -0x300(%RBP),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0x2f0(%RBP),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0x2e0(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
JNE 443b60 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xfb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
JMP 443760 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xbb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source file and lines	MultiBsplineRef.hpp:227-262
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:61
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:227,234-262

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.33 to 8.33 cycles (1.84x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

31% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

34% of SSE/AVX loads are used in vector version.
42% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
29% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 15.33 to 13.83 cycles (1.11x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 2 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 11 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

6: multiply

The binary loop is loading 340 bytes (42 double precision FP elements). The binary loop is storing 160 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	82
nb uops	83
loop length	489
used x86 registers	10
used mmx registers	0
used xmm registers	15
used ymm registers	0
used zmm registers	0
nb stack references	27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.83 cycles
front end	13.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.00	4.00	3.75	3.75	2.50	15.33	15.33	15.33	3.00	3.00	3.00	3.00	3.00	3.00
cycles	4.00	4.00	3.75	3.75	2.50	15.33	15.33	15.33	3.00	3.00	3.00	3.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	13.83
Dispatch	15.33
Data deps.	0.00
Overall L1	15.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	54%
load	60%
store	100%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

INT+FP

all	31%
load	34%
store	42%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	29%

Vector efficiency ratios

INT

all	12%
load	11%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	19%
load	20%
store	25%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	16%
load	16%
store	17%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.33 cycles. At this rate:

23% of peak load performance is reached (22.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (10.43 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4437bc

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV -0xa8(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA 0x1(%R12),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x98(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R11,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x128(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %RDI,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x130(%RBP),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %RDI,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RDI,-0x118(%RBP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD %RDI,-0x120(%RBP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD %RDI,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RDI,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R15,-0xa0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %RDI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x3,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R8,-0xa8(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JE 443650 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xaa0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R11,-0x128(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %R13,-0x130(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
CMPL $0,-0x70(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV -0xa0(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JLE 443760 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xbb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV -0xa8(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSD -0x410(%RBP,%RDI,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVAPD %XMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULSD -0x200(%RBP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM6,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVSD -0x1f8(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MULSD %XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVSD -0x1f0(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MULSD %XMM1,%XMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVSD -0x2a0(%RBP,%RDI,8),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVAPD %XMM13,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULSD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULSD %XMM1,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVSD -0x260(%RBP,%RDI,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MULSD %XMM1,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOV -0x90(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
TEST %RDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVAPD %XMM3,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
JE 443b40 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xf90>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RAX,-0x208(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %RSI,-0x210(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVAPD %XMM7,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKLPD %XMM7,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVAPD %XMM1,-0x3b0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD %XMM2,-0x2f0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
UNPCKLPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVAPD %XMM2,-0x150(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
UNPCKLPD %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVAPD -0x2d0(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD %XMM15,-0x2e0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
UNPCKLPD %XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVAPD %XMM13,-0x300(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
UNPCKLPD %XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVAPD %XMM6,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKLPD %XMM6,%XMM12	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV -0x50(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x118(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x120(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x130(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x128(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x70(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP %RDI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVAPD -0xd0(%RBP),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0x240(%RBP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0x80(%RBP),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0x60(%RBP),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0xc0(%RBP),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOV -0x210(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x208(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0xa0(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVAPD -0x300(%RBP),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0x2f0(%RBP),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0x2e0(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
JNE 443b60 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xfb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
JMP 443760 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0xbb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Report Configuration

Vectorization

Details

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code