OV - exec - Loop 826

	Loop Id: 826	Module: exec	Source: MultiBsplineRef.hpp:276-286	Coverage: 0.17%

0x443e90 MOVUPD	(%R15,%R10,8),%XMM15    [9]

0x443e96 MULPD	%XMM6,%XMM15

0x443e9b MOVUPD	%XMM15,(%R15,%R10,8)    [9]

0x443ea1 MOVUPD	(%RDX,%R10,8),%XMM15    [3]

0x443ea7 MULPD	%XMM7,%XMM15

0x443eac MOVUPD	%XMM15,(%RDX,%R10,8)    [3]

0x443eb2 MOVUPD	(%RCX,%R10,8),%XMM15    [5]

0x443eb8 MULPD	%XMM8,%XMM15

0x443ebd MOVUPD	%XMM15,(%RCX,%R10,8)    [5]

0x443ec3 MOVUPD	(%RBX,%R10,8),%XMM15    [1]

0x443ec9 MULPD	%XMM9,%XMM15

0x443ece MOVUPD	%XMM15,(%RBX,%R10,8)    [1]

0x443ed4 MOVUPD	(%RDI,%R10,8),%XMM15    [2]

0x443eda MULPD	%XMM10,%XMM15

0x443edf MOVUPD	%XMM15,(%RDI,%R10,8)    [2]

0x443ee5 MOVUPD	(%RSI,%R10,8),%XMM15    [6]

0x443eeb MULPD	%XMM11,%XMM15

0x443ef0 MOVUPD	%XMM15,(%RSI,%R10,8)    [6]

0x443ef6 MOVUPD	(%R9,%R10,8),%XMM15    [7]

0x443efc MULPD	%XMM12,%XMM15

0x443f01 MOVUPD	%XMM15,(%R9,%R10,8)    [7]

0x443f07 MOVUPD	(%R8,%R10,8),%XMM15    [8]

0x443f0d MULPD	%XMM13,%XMM15

0x443f12 MOVUPD	%XMM15,(%R8,%R10,8)    [8]

0x443f18 MOVUPD	(%RAX,%R10,8),%XMM15    [4]

0x443f1e MULPD	%XMM14,%XMM15

0x443f23 MOVUPD	%XMM15,(%RAX,%R10,8)    [4]

0x443f29 ADD	$0x2,%R10

0x443f2d CMP	%R14,%R10

0x443f30 JL	443e90

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 276 - 286

--------------------------------------------------------------------------------

276:   for (int n = 0; n < num_splines; n++)

277:   {

278:     gx[n] *= dxInv;

279:     gy[n] *= dyInv;

280:     gz[n] *= dzInv;

281:     hxx[n] *= dxx;

282:     hyy[n] *= dyy;

283:     hzz[n] *= dzz;

284:     hxy[n] *= dxy;

285:     hxz[n] *= dxz;

286:     hyz[n] *= dyz;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.24
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source	MultiBsplineRef.hpp:276-286
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	2.25
Front-end cycles	4.83
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	6.00
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	4.50
P12 cycles	4.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	29.00
Nb loads	9.00
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	3.00
Nb FLOP add-sub	0.00
Nb FLOP mul	18.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	144.00
Stride 0	0.00
Stride 1	9.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.24
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source	MultiBsplineRef.hpp:276-286
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	2.25
Front-end cycles	4.83
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	6.00
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	4.50
P12 cycles	4.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	29.00
Nb loads	9.00
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	3.00
Nb FLOP add-sub	0.00
Nb FLOP mul	18.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	144.00
Stride 0	0.00
Stride 1	9.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source file and lines	MultiBsplineRef.hpp:276-286
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:276-286.

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 6.00 to 2.25 cycles (2.67x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 4.83 cycles (1.24x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Vector unaligned load/store instructions

Detected 18 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 18 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

9 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 18 FP arithmetical operations:

18: multiply

The binary loop is loading 144 bytes (18 double precision FP elements). The binary loop is storing 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	30
nb uops	29
loop length	166
used x86 registers	11
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.83 cycles
front end	4.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	6.00	6.00	6.00	4.50	4.50	0.00	0.00	4.50	4.50
cycles	0.50	0.50	0.25	0.25	0.50	6.00	6.00	6.00	4.50	4.50	0.00	0.00	4.50	4.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.83
Dispatch	6.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
37% of peak store performance is reached (24.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 443e90

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
MOVUPD (%R15,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM6,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%R15,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVUPD (%RDX,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM7,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%RDX,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVUPD (%RCX,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM8,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%RCX,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVUPD (%RBX,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM9,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%RBX,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVUPD (%RDI,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM10,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%RDI,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVUPD (%RSI,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM11,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%RSI,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVUPD (%R9,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM12,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVUPD (%R8,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%R8,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVUPD (%RAX,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%RAX,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
ADD $0x2,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R14,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JL 443e90 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x12e0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source file and lines	MultiBsplineRef.hpp:276-286
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 6.00 to 2.25 cycles (2.67x speedup).

Details

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 4.83 cycles (1.24x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Vector unaligned load/store instructions

Detected 18 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 18 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

9 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 18 FP arithmetical operations:

18: multiply

The binary loop is loading 144 bytes (18 double precision FP elements). The binary loop is storing 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	30
nb uops	29
loop length	166
used x86 registers	11
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.83 cycles
front end	4.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	6.00	6.00	6.00	4.50	4.50	0.00	0.00	4.50	4.50
cycles	0.50	0.50	0.25	0.25	0.50	6.00	6.00	6.00	4.50	4.50	0.00	0.00	4.50	4.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.83
Dispatch	6.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
37% of peak store performance is reached (24.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 443e90

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
MOVUPD (%R15,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM6,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%R15,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVUPD (%RDX,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM7,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%RDX,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVUPD (%RCX,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM8,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%RCX,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVUPD (%RBX,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM9,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%RBX,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVUPD (%RDI,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM10,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%RDI,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVUPD (%RSI,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM11,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%RSI,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVUPD (%R9,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM12,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVUPD (%R8,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%R8,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVUPD (%RAX,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MULPD %XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM15,(%RAX,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
ADD $0x2,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R14,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JL 443e90 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x12e0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code