OV - exec - Loop 823

	Loop Id: 823	Module: exec	Source: einspline_spo_ref.hpp:223-227 [...]	Coverage: 0.4%

0x4440b0 MOV	0x310(%RBX),%RDX    [15]

0x4440b7 MOV	(%RDX,%R10,8),%RDX    [10]

0x4440bb MOVSD	(%RDX,%R11,8),%XMM0    [11]

0x4440c1 MOV	0x18(%R13),%RDX    [12]

0x4440c5 ADD	%R8,%RDX

0x4440c8 MOVSD	%XMM0,(%RDX,%R11,8)    [7]

0x4440ce MOV	0x328(%RBX),%RDX    [15]

0x4440d5 LEA	(%RCX,%RCX,4),%RSI

0x4440d9 MOV	0x18(%RDX,%RSI,1),%RBX    [16]

0x4440de MOVSXD	0x8(%RDX,%RSI,1),%RDX    [16]

0x4440e3 MOVSD	(%RBX,%R11,8),%XMM0    [1]

0x4440e9 LEA	(%R11,%RDX,1),%R14

0x4440ed MOVSD	(%RBX,%R14,8),%XMM1    [6]

0x4440f3 LEA	(%R11,%RDX,2),%RDX

0x4440f7 MOVSD	(%RBX,%RDX,8),%XMM2    [2]

0x4440fc MOV	0x18(%R12),%RDX    [3]

0x444101 MOVSD	%XMM0,-0x10(%RDX,%R9,8)    [9]

0x444108 MOVSD	%XMM1,-0x8(%RDX,%R9,8)    [9]

0x44410f MOVSD	%XMM2,(%RDX,%R9,8)    [9]

0x444115 MOV	-0x48(%RBP),%RDX    [14]

0x444119 MOV	0x340(%RDX),%RDX    [4]

0x444120 MOV	0x18(%RDX,%RSI,1),%RDX    [17]

0x444125 MOVSD	(%RDX,%R11,8),%XMM0    [8]

0x44412b MOV	0x18(%R15),%RDX    [13]

0x44412f ADD	%R8,%RDX

0x444132 MOVSD	%XMM0,(%RDX,%R11,8)    [5]

0x444138 MOV	-0x48(%RBP),%RDX    [14]

0x44413c MOV	0x8(%RDX),%EDX    [4]

0x44413f MOV	-0x48(%RBP),%RSI    [14]

0x444143 MOV	0x40(%RSI),%ESI    [4]

0x444146 MOV	%ESI,%EBX

0x444148 IMUL	%EAX,%EBX

0x44414b CMP	%EBX,%EDX

0x44414d CMOVL	%EDX,%EBX

0x444150 MOVSXD	%EBX,%RBX

0x444153 ADD	$0x3,%R9

0x444157 LEA	(%RDI,%R11,1),%R14

0x44415b INC	%R14

0x44415e INC	%R11

0x444161 CMP	%RBX,%R14

0x444164 MOV	-0x48(%RBP),%RBX    [14]

0x444168 JL	4440b0

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 271

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

[...]

271:   inline T* restrict data(size_t i) { return myData + i * nGhosts; }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 145 - 145

--------------------------------------------------------------------------------

145:       X[i] = base[i * offset];

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 223

--------------------------------------------------------------------------------

223:     return X[i];

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1046

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 235 - 235

--------------------------------------------------------------------------------

235:       if (__b < __a)

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 223 - 227

--------------------------------------------------------------------------------

223:       for (int j = first; j < std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize); j++)

224:       {

225:         psi_v[j]   = psi[i][j - first];

226:         dpsi_v[j]  = grad[i][j - first];

227:         d2psi_v[j] = hess[i].data(0)[j - first];

Path /

Metric	Value
CQA speedup if no scalar integer	2.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.62
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.24
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source	VectorSoAContainer.h:231-231,VectorSoAContainer.h:271-271,TinyVector.h:145-145,OhmmsVector.h:223-223,stl_vector.h:1046-1046,stl_algobase.h:235-235,einspline_spo_ref.hpp:223-227
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.67
CQA cycles if no scalar integer	4.33
CQA cycles if FP arith vectorized	8.67
CQA cycles if fully vectorized	1.88
Front-end cycles	7.00
DIV/SQRT cycles	4.00
P0 cycles	4.00
P1 cycles	3.75
P2 cycles	3.75
P3 cycles	0.50
P4 cycles	8.67
P5 cycles	8.67
P6 cycles	8.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	2.50
P12 cycles	2.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	21.00
Nb stores	5.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.62
Bytes prefetched	0.00
Bytes loaded	156.00
Bytes stored	40.00
Stride 0	4.00
Stride 1	1.00
Stride n	1.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.93
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	2.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.62
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.24
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source	VectorSoAContainer.h:231-231,VectorSoAContainer.h:271-271,TinyVector.h:145-145,OhmmsVector.h:223-223,stl_vector.h:1046-1046,stl_algobase.h:235-235,einspline_spo_ref.hpp:223-227
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.67
CQA cycles if no scalar integer	4.33
CQA cycles if FP arith vectorized	8.67
CQA cycles if fully vectorized	1.88
Front-end cycles	7.00
DIV/SQRT cycles	4.00
P0 cycles	4.00
P1 cycles	3.75
P2 cycles	3.75
P3 cycles	0.50
P4 cycles	8.67
P5 cycles	8.67
P6 cycles	8.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	2.50
P12 cycles	2.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	21.00
Nb stores	5.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.62
Bytes prefetched	0.00
Bytes loaded	156.00
Bytes stored	40.00
Stride 0	4.00
Stride 1	1.00
Stride n	1.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.93
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source file and lines	einspline_spo_ref.hpp:223-227
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,271
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:235
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:223-227

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.67 to 4.33 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.67 to 1.87 cycles (4.62x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 8.67 to 7.00 cycles (1.24x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 156 bytes. The binary loop is storing 40 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	42
nb uops	42
loop length	190
used x86 registers	15
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.00	4.00	3.75	3.75	0.50	8.67	8.67	8.67	0.00	0.00	0.00	0.00	2.50	2.50
cycles	4.00	4.00	3.75	3.75	0.50	8.67	8.67	8.67	0.00	0.00	0.00	0.00	2.50	2.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.00
Dispatch	8.67
Data deps.	1.00
Overall L1	8.67

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.67 cycles. At this rate:

18% of peak load performance is reached (18.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.62 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4440b0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
MOV 0x310(%RBX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RDX,%R10,8),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOVSD (%RDX,%R11,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV 0x18(%R13),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD %R8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%RDX,%R11,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOV 0x328(%RBX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%RCX,%RCX,4),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x18(%RDX,%RSI,1),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOVSXD 0x8(%RDX,%RSI,1),%RDX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
MOVSD (%RBX,%R11,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
LEA (%R11,%RDX,1),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD (%RBX,%R14,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
LEA (%R11,%RDX,2),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD (%RBX,%RDX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV 0x18(%R12),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOVSD %XMM0,-0x10(%RDX,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM1,-0x8(%RDX,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM2,(%RDX,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOV -0x48(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x340(%RDX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x18(%RDX,%RSI,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOVSD (%RDX,%R11,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV 0x18(%R15),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD %R8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%RDX,%R11,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOV -0x48(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x8(%RDX),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x48(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x40(%RSI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %ESI,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %EAX,%EBX	1	0	1	0	0	0	0	0	0	0	0	3	1
CMP %EBX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMOVL %EDX,%EBX	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
MOVSXD %EBX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD $0x3,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RDI,%R11,1),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
INC %R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
INC %R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP %RBX,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV -0x48(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
JL 4440b0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1500>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source file and lines	einspline_spo_ref.hpp:223-227
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,271
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:235
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:223-227

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.67 to 4.33 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 8.67 to 7.00 cycles (1.24x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 156 bytes. The binary loop is storing 40 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	42
nb uops	42
loop length	190
used x86 registers	15
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.00	4.00	3.75	3.75	0.50	8.67	8.67	8.67	0.00	0.00	0.00	0.00	2.50	2.50
cycles	4.00	4.00	3.75	3.75	0.50	8.67	8.67	8.67	0.00	0.00	0.00	0.00	2.50	2.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.00
Dispatch	8.67
Data deps.	1.00
Overall L1	8.67

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.67 cycles. At this rate:

18% of peak load performance is reached (18.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.62 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4440b0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
MOV 0x310(%RBX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RDX,%R10,8),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOVSD (%RDX,%R11,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV 0x18(%R13),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD %R8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%RDX,%R11,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOV 0x328(%RBX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%RCX,%RCX,4),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x18(%RDX,%RSI,1),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOVSXD 0x8(%RDX,%RSI,1),%RDX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
MOVSD (%RBX,%R11,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
LEA (%R11,%RDX,1),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD (%RBX,%R14,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
LEA (%R11,%RDX,2),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD (%RBX,%RDX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV 0x18(%R12),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOVSD %XMM0,-0x10(%RDX,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM1,-0x8(%RDX,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM2,(%RDX,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOV -0x48(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x340(%RDX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x18(%RDX,%RSI,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOVSD (%RDX,%R11,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV 0x18(%R15),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD %R8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%RDX,%R11,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOV -0x48(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x8(%RDX),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x48(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x40(%RSI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %ESI,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %EAX,%EBX	1	0	1	0	0	0	0	0	0	0	0	3	1
CMP %EBX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMOVL %EDX,%EBX	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
MOVSXD %EBX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD $0x3,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RDI,%R11,1),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
INC %R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
INC %R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP %RBX,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV -0x48(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
JL 4440b0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1500>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code