OV - exec - Loop 820

	Loop Id: 820	Module: exec	Source: MultiBsplineRef.hpp:64-71	Coverage: 0.02%

0x4429e0 LEA	0x1(%RCX),%RSI

0x4429e4 ADD	%R10,%RDX

0x4429e7 ADD	%R10,%R8

0x4429ea ADD	%R10,%R9

0x4429ed ADD	%R10,%R12

0x4429f0 CMP	$0x3,%RCX

0x4429f4 MOV	%RSI,%RCX

0x4429f7 JE	442970

0x4429fd TEST	%R14D,%R14D

0x442a00 JE	4429e0

0x442a02 MOVSD	-0x130(%RBP,%RCX,8),%XMM8

0x442a0c MULSD	%XMM7,%XMM8

0x442a11 CMP	$0x2,%R15

0x442a15 JB	442a8c

0x442a17 MOVAPD	%XMM8,%XMM9

0x442a1c UNPCKLPD	%XMM8,%XMM9

0x442a21 MOV	-0x108(%RBP),%RSI

0x442a28 XOR	%EDI,%EDI

0x442a2a NOPW	(%RAX,%RAX,1)

  (821) 0x442a30 MOVUPD	(%R12,%RDI,1),%XMM10

  (821) 0x442a36 MULPD	%XMM4,%XMM10

  (821) 0x442a3b MOVUPD	(%R9,%RDI,1),%XMM11

  (821) 0x442a41 MULPD	%XMM3,%XMM11

  (821) 0x442a46 ADDPD	%XMM10,%XMM11

  (821) 0x442a4b MOVUPD	(%R8,%RDI,1),%XMM10

  (821) 0x442a51 MULPD	%XMM5,%XMM10

  (821) 0x442a56 MOVUPD	(%RDX,%RDI,1),%XMM12

  (821) 0x442a5c MULPD	%XMM6,%XMM12

  (821) 0x442a61 ADDPD	%XMM10,%XMM12

  (821) 0x442a66 ADDPD	%XMM11,%XMM12

  (821) 0x442a6b MULPD	%XMM9,%XMM12

  (821) 0x442a70 MOVUPD	(%R13,%RDI,1),%XMM10

  (821) 0x442a77 ADDPD	%XMM12,%XMM10

  (821) 0x442a7c MOVUPD	%XMM10,(%R13,%RDI,1)

  (821) 0x442a83 ADD	$0x10,%RDI

  (821) 0x442a87 DEC	%RSI

  (821) 0x442a8a JNE	442a30

0x442a8c CMP	%R15,%RBX

0x442a8f JAE	4429e0

0x442a95 MOV	-0x50(%RBP),%RSI

0x442a99 IMUL	%RCX,%RSI

0x442a9d ADD	%R11,%RSI

0x442aa0 MOV	-0x60(%RBP),%RDI

0x442aa4 ADD	%RSI,%RDI

0x442aa7 MOVSD	(%RAX,%RDI,8),%XMM9

0x442aad MOV	-0x38(%RBP),%RDI

0x442ab1 ADD	%RSI,%RDI

0x442ab4 MOVHPD	(%RAX,%RDI,8),%XMM9

0x442aba MOV	-0x30(%RBP),%RDI

0x442abe ADD	%RSI,%RDI

0x442ac1 ADD	-0x90(%RBP),%RSI

0x442ac8 MOVAPD	%XMM2,%XMM10

0x442acd MOVHPD	(%RAX,%RSI,8),%XMM10

0x442ad3 MOVSD	(%RAX,%RDI,8),%XMM11

0x442ad9 UNPCKLPD	%XMM0,%XMM11

0x442ade MULPD	%XMM11,%XMM10

0x442ae3 MULPD	%XMM1,%XMM9

0x442ae8 ADDPD	%XMM10,%XMM9

0x442aed MOVAPD	%XMM9,%XMM10

0x442af2 UNPCKHPD	%XMM9,%XMM10

0x442af7 ADDSD	%XMM9,%XMM10

0x442afc MULSD	%XMM10,%XMM8

0x442b01 ADDSD	(%R13,%RBX,8),%XMM8

0x442b08 MOVSD	%XMM8,(%R13,%RBX,8)

0x442b0f JMP	4429e0

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 64 - 71

--------------------------------------------------------------------------------

64:     for (size_t j = 0; j < 4; j++)

65:     {

66:       const T pre00           = a[i] * b[j];

67:       const T* restrict coefs = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs;

68:       for (size_t n = 0; n < num_splines; n++)

69:         vals[n] += pre00 *

70:             (c[0] * coefs[n] + c[1] * coefs[n + zs] + c[2] * coefs[n + 2 * zs] +

71:              c[3] * coefs[n + 3 * zs]);

Path /

Metric	Value
CQA speedup if no scalar integer	1.59
CQA speedup if FP arith vectorized	2.18
CQA speedup if fully vectorized	7.36
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.70
Bottlenecks	micro-operation queue,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE
Source	MultiBsplineRef.hpp:64-71
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.67
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	3.52
CQA cycles if fully vectorized	1.04
Front-end cycles	7.67
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	4.25
P2 cycles	4.25
P3 cycles	2.50
P4 cycles	4.33
P5 cycles	4.33
P6 cycles	4.33
P7 cycles	2.00
P8 cycles	3.33
P9 cycles	3.50
P10 cycles	3.17
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	46.00
Nb loads	12.00
Nb stores	1.00
Nb stack references	6.00
FLOP/cycle	1.30
Nb FLOP add-sub	4.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.57
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	22.22
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	50.00
Vectorization ratio add_sub	14.29
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	30.00
Vector-efficiency ratio all	15.05
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	18.75
Vector-efficiency ratio add_sub	14.29
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Metric	Value
CQA speedup if no scalar integer	1.59
CQA speedup if FP arith vectorized	2.18
CQA speedup if fully vectorized	7.36
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.70
Bottlenecks	micro-operation queue,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE
Source	MultiBsplineRef.hpp:64-71
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.67
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	3.52
CQA cycles if fully vectorized	1.04
Front-end cycles	7.67
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	4.25
P2 cycles	4.25
P3 cycles	2.50
P4 cycles	4.33
P5 cycles	4.33
P6 cycles	4.33
P7 cycles	2.00
P8 cycles	3.33
P9 cycles	3.50
P10 cycles	3.17
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	46.00
Nb loads	12.00
Nb stores	1.00
Nb stack references	6.00
FLOP/cycle	1.30
Nb FLOP add-sub	4.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.57
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	22.22
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	50.00
Vectorization ratio add_sub	14.29
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	30.00
Vector-efficiency ratio all	15.05
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	18.75
Vector-efficiency ratio add_sub	14.29
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE
Source file and lines	MultiBsplineRef.hpp:64-71
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:64-71.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.67 to 4.83 cycles (1.59x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.67 to 1.04 cycles (7.36x speedup).

Details

22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
14% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
30% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 2 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 10 FP arithmetical operations:

4: addition or subtraction
6: multiply

The binary loop is loading 96 bytes (12 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	47
nb uops	46
loop length	216
used x86 registers	15
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	6
ADD-SUB / MUL ratio	0.75

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.67 cycles
front end	7.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.50	4.50	4.25	4.25	2.50	4.33	4.33	4.33	2.00	3.33	3.50	3.17	0.50	0.50
cycles	4.50	4.50	4.25	4.25	2.50	4.33	4.33	4.33	2.00	3.33	3.50	3.17	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.67
Dispatch	4.50
Overall L1	7.67

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	31%
load	0%
store	0%
mul	50%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	22%
load	0%
store	0%
mul	50%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	16%
load	12%
store	12%
mul	18%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	15%
load	12%
store	12%
mul	18%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.67 cycles. At this rate:

13% of peak load performance is reached (12.52 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.04 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.67 to 4.50 cycles (1.70x speedup).

ASM code

In the binary file, the address of the loop is: 4429fd

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
LEA 0x1(%RCX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R10,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R10,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R10,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x3,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JE 442970 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x650>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
TEST %R14D,%R14D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 4429e0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x6c0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSD -0x130(%RBP,%RCX,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MULSD %XMM7,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
CMP $0x2,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JB 442a8c <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x76c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVAPD %XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKLPD %XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOV -0x108(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
CMP %R15,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 4429e0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x6c0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV -0x50(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RCX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R11,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x60(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %RSI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSD (%RAX,%RDI,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV -0x38(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %RSI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVHPD (%RAX,%RDI,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
MOV -0x30(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %RSI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD -0x90(%RBP),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOVAPD %XMM2,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVHPD (%RAX,%RSI,8),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
MOVSD (%RAX,%RDI,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
UNPCKLPD %XMM0,%XMM11	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MULPD %XMM11,%XMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKHPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
ADDSD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULSD %XMM10,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDSD (%R13,%RBX,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVSD %XMM8,(%R13,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
JMP 4429e0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x6c0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE
Source file and lines	MultiBsplineRef.hpp:64-71
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:64-71.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.67 to 4.83 cycles (1.59x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
14% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
30% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 2 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 10 FP arithmetical operations:

4: addition or subtraction
6: multiply

The binary loop is loading 96 bytes (12 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	47
nb uops	46
loop length	216
used x86 registers	15
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	6
ADD-SUB / MUL ratio	0.75

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.67 cycles
front end	7.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.50	4.50	4.25	4.25	2.50	4.33	4.33	4.33	2.00	3.33	3.50	3.17	0.50	0.50
cycles	4.50	4.50	4.25	4.25	2.50	4.33	4.33	4.33	2.00	3.33	3.50	3.17	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.67
Dispatch	4.50
Overall L1	7.67

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	31%
load	0%
store	0%
mul	50%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	22%
load	0%
store	0%
mul	50%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	16%
load	12%
store	12%
mul	18%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	15%
load	12%
store	12%
mul	18%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.67 cycles. At this rate:

13% of peak load performance is reached (12.52 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.04 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4429fd

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
LEA 0x1(%RCX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R10,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R10,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R10,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R10,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x3,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JE 442970 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x650>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
TEST %R14D,%R14D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 4429e0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x6c0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSD -0x130(%RBP,%RCX,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MULSD %XMM7,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
CMP $0x2,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JB 442a8c <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x76c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVAPD %XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKLPD %XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOV -0x108(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
CMP %R15,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JAE 4429e0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x6c0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV -0x50(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %RCX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R11,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x60(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %RSI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSD (%RAX,%RDI,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV -0x38(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %RSI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVHPD (%RAX,%RDI,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
MOV -0x30(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %RSI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD -0x90(%RBP),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOVAPD %XMM2,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVHPD (%RAX,%RSI,8),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
MOVSD (%RAX,%RDI,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
UNPCKLPD %XMM0,%XMM11	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MULPD %XMM11,%XMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKHPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
ADDSD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULSD %XMM10,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDSD (%R13,%RBX,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVSD %XMM8,(%R13,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
JMP 4429e0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x6c0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code