OV - exec - Loop 80

	Loop Id: 80	Module: exec	Source: NonLocalPP.hpp:126-135 [...]	Coverage: 0.07%

0x411150 INC	%R14

0x411153 CMP	%R14,0x260(%RAX)

0x41115a JBE	4110f0

0x41115c MOV	(%R15),%RCX

0x41115f MOVSD	(%RCX,%R14,8),%XMM0

0x411165 UCOMISD	(%R12),%XMM0

0x41116b JAE	411150

0x41116d MOV	0x13f0(%R12),%RCX

0x411175 SUB	0x13e8(%R12),%RCX

0x41117d SHR	$0x3,%RCX

0x411181 IMUL	$-0x55555555,%ECX,%ECX

0x411187 TEST	%ECX,%ECX

0x411189 JLE	41124d

0x41118f MOV	$0x10,%EAX

0x411194 MOV	-0x38(%RBP),%RCX

0x411198 LEA	(%RCX,%RCX,2),%RCX

0x41119c XOR	%EDX,%EDX

0x41119e MOV	-0x30(%RBP),%R9

0x4111a2 NOPW	%CS:(%RAX,%RAX,1)

  (81) 0x4111b0 MOV	(%R15),%RDI

  (81) 0x4111b3 MOVSD	(%RDI,%R14,8),%XMM0

  (81) 0x4111b9 MOVSD	(%R9,%RAX,1),%XMM1

  (81) 0x4111bf MULSD	%XMM0,%XMM1

  (81) 0x4111c3 MOV	(%RBX),%R10

  (81) 0x4111c6 MOVSXD	-0x10(%RBX),%RDI

  (81) 0x4111ca LEA	(%R14,%RDI,2),%R8

  (81) 0x4111ce ADDSD	(%R10,%R8,8),%XMM1

  (81) 0x4111d4 ADD	%R14,%RDI

  (81) 0x4111d7 MOVSD	(%R10,%R14,8),%XMM2

  (81) 0x4111dd MOVHPD	(%R10,%RDI,8),%XMM2

  (81) 0x4111e3 MOV	0x40(%RSI),%RDI

  (81) 0x4111e7 ADDSD	0x10(%RDI,%RCX,8),%XMM1

  (81) 0x4111ed MOVUPD	-0x10(%R9,%RAX,1),%XMM3

  (81) 0x4111f4 UNPCKLPD	%XMM0,%XMM0

  (81) 0x4111f8 MULPD	%XMM3,%XMM0

  (81) 0x4111fc MOVUPD	(%RDI,%RCX,8),%XMM3

  (81) 0x411201 MOV	-0x60(%RBP),%RDI

  (81) 0x411205 ADDPD	%XMM2,%XMM3

  (81) 0x411209 ADDPD	%XMM0,%XMM3

  (81) 0x41120d MOVUPD	%XMM3,-0x10(%RDI,%RAX,1)

  (81) 0x411213 MOVSD	%XMM1,(%RDI,%RAX,1)

  (81) 0x411218 INC	%RDX

  (81) 0x41121b MOV	0x13f0(%R12),%RDI

  (81) 0x411223 SUB	0x13e8(%R12),%RDI

  (81) 0x41122b SHR	$0x3,%RDI

  (81) 0x41122f IMUL	$-0x55555555,%EDI,%EDI

  (81) 0x411235 MOVSXD	%EDI,%RDI

  (81) 0x411238 ADD	$0x18,%RAX

  (81) 0x41123c CMP	%RDI,%RDX

  (81) 0x41123f JL	4111b0

0x411245 MOV	0x1418(%R12),%RAX

0x41124d MOV	0x18(%RAX),%RAX

0x411251 MOVSXD	(%RAX,%R14,4),%RAX

0x411255 MOV	0x1400(%R12),%RCX

0x41125d MOV	(%RCX,%RAX,8),%R13

0x411261 MOV	%R13,%RDI

0x411264 MOV	-0x38(%RBP),%RDX

0x411268 LEA	-0x60(%RBP),%RCX

0x41126c MOV	$0x1,%R8D

0x411272 MOV	%R14D,%R9D

0x411275 CALL	4052e0 <@plt>

0x41127a MOV	-0x90(%RBP),%RDI

0x411281 MOV	%R13,%RSI

0x411284 LEA	-0x80(%RBP),%RDX

0x411288 CALL	405610 <@plt>

0x41128d MOV	0x1418(%R12),%RAX

0x411295 MOV	-0x88(%RBP),%RSI

0x41129c JMP	411150

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 231

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 145 - 170

--------------------------------------------------------------------------------

145:       X[i] = base[i * offset];

[...]

170:   inline const Type_t& operator[](unsigned int i) const { return X[i]; }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 229 - 229

--------------------------------------------------------------------------------

229:     return X[i];

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 919 - 1046

--------------------------------------------------------------------------------

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1046: 	return *(this->_M_impl._M_start + __n);

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 43 - 63

--------------------------------------------------------------------------------

43:     return (a + b);

[...]

63:     return (a * b);

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h: 173 - 173

--------------------------------------------------------------------------------

173:       pointer    _M_ptr() const { return std::get<0>(_M_t); }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp: 126 - 135

--------------------------------------------------------------------------------

126:       for (int iat = 0; iat < ions_ref.getTotalNum(); ++iat)

127:       {

128:         //due to < Rmax condition, the actually iteration iat is [0,2] in a real simulation

129:         if (dist[iat] < Rmax)

130:         {

131:           for (int k = 0; k < size(); k++)

132:             virtualPos[k] = dist[iat] * rOnSphere[k] + displ[iat] + els.R[jel];

133:           auto& VP = *VPs[ions_ref.GroupID[iat]];

134:           VP.makeMoves(els, jel, virtualPos, true, iat);

135:           wf.evaluateRatios(VP, ratios);

Path /

Metric	Value
CQA speedup if no scalar integer	3.20
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.44
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks
Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source	TinyVector.h:170-170,OhmmsVector.h:229-229,stl_vector.h:919-919,stl_vector.h:1046-1046,unique_ptr.h:173-173,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.44
CQA cycles if no scalar integer	1.39
CQA cycles if FP arith vectorized	4.44
CQA cycles if fully vectorized	1.00
Front-end cycles	4.44
DIV/SQRT cycles	2.67
P0 cycles	2.58
P1 cycles	2.58
P2 cycles	2.50
P3 cycles	2.33
P4 cycles	4.33
P5 cycles	4.33
P6 cycles	4.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.67
Nb uops	26.67
Nb loads	11.67
Nb stores	0.00
Nb stack references	3.67
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.31
Bytes prefetched	0.00
Bytes loaded	90.67
Bytes stored	0.00
Stride 0	3.00
Stride 1	1.33
Stride n	3.00
Stride unknown	1.33
Stride indirect	0.33
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.64
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.91

Metric	Value
CQA speedup if no scalar integer	1.14
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	micro-operation queue, P5, P6, P7,
Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source	TinyVector.h:170-170,OhmmsVector.h:229-229,stl_vector.h:919-919,stl_vector.h:1046-1046,unique_ptr.h:173-173,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.33
CQA cycles if no scalar integer	1.17
CQA cycles if FP arith vectorized	1.33
CQA cycles if fully vectorized	0.33
Front-end cycles	1.33
DIV/SQRT cycles	1.00
P0 cycles	0.75
P1 cycles	0.75
P2 cycles	0.50
P3 cycles	1.00
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	7.00
Nb uops	8.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	1.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	4.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.46
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source	TinyVector.h:170-170,OhmmsVector.h:229-229,stl_vector.h:919-919,stl_vector.h:1046-1046,unique_ptr.h:173-173,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.50
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	6.50
CQA cycles if fully vectorized	1.46
Front-end cycles	6.50
DIV/SQRT cycles	3.75
P0 cycles	3.75
P1 cycles	3.75
P2 cycles	3.75
P3 cycles	3.00
P4 cycles	6.33
P5 cycles	6.33
P6 cycles	6.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	39.00
Nb loads	17.00
Nb stores	0.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.31
Bytes prefetched	0.00
Bytes loaded	132.00
Bytes stored	0.00
Stride 0	4.00
Stride 1	2.00
Stride n	5.00
Stride unknown	4.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.06
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.82

Metric	Value
CQA speedup if no scalar integer	3.67
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.55
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source	TinyVector.h:170-170,OhmmsVector.h:229-229,stl_vector.h:919-919,stl_vector.h:1046-1046,unique_ptr.h:173-173,NonLocalPP.hpp:126-126,NonLocalPP.hpp:129-135
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.50
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	1.21
Front-end cycles	5.50
DIV/SQRT cycles	3.25
P0 cycles	3.25
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.00
P4 cycles	5.33
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	33.00
Nb loads	14.00
Nb stores	0.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.64
Bytes prefetched	0.00
Bytes loaded	108.00
Bytes stored	0.00
Stride 0	3.00
Stride 1	1.00
Stride n	3.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.36
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.42

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source file and lines	NonLocalPP.hpp:126-135
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145,170
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h:173
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.44 to 1.00 cycles (4.44x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

UCOMISD: 1 occurrences

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 90 bytes (11 double precision FP elements).

General properties

nb instructions	24.67
nb uops	26.67
loop length	121.33
used x86 registers	9.67
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	3.67

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	4.44 cycles
front end	4.44 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.67	2.58	2.58	2.50	2.33	4.33	4.33	4.33	0.00	0.00	0.50	0.50	0.50	0.50
cycles	2.67	2.58	2.58	2.50	2.33	4.33	4.33	4.33	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.44
Dispatch	4.33
Data deps.	1.00
Overall L1	4.44

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.44 cycles. At this rate:

22% of peak load performance is reached (21.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source file and lines	NonLocalPP.hpp:126-135
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145,170
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h:173
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.33 to 1.17 cycles (1.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 1.33 to 0.33 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.33 to 1.00 cycles (1.33x speedup).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

UCOMISD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes (4 double precision FP elements).

General properties

nb instructions	7
nb uops	8
loop length	29
used x86 registers	5
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.33 cycles
front end	1.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	0.75	0.75	0.50	1.00	1.33	1.33	1.33	0.00	0.00	0.50	0.50	0.50	0.50
cycles	1.00	0.75	0.75	0.50	1.00	1.33	1.33	1.33	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.33
Dispatch	1.33
Data deps.	1.00
Overall L1	1.33

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.33 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.33 to 1.00 cycles (1.33x speedup).

ASM code

In the binary file, the address of the loop is: 41115c

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
INC %R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R14,0x260(%RAX)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
JBE 4110f0 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x5b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV (%R15),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOVSD (%RCX,%R14,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD (%R12),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0.50	0.50	7	1
JAE 411150 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x610>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source file and lines	NonLocalPP.hpp:126-135
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145,170
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h:173
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 1.50 cycles (4.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

UCOMISD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)
Constant non-unit stride: 5 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 132 bytes (16 double precision FP elements).

General properties

nb instructions	37
nb uops	39
loop length	188
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.75	3.75	3.75	3.75	3.00	6.33	6.33	6.33	0.00	0.00	0.50	0.50	0.50	0.50
cycles	3.75	3.75	3.75	3.75	3.00	6.33	6.33	6.33	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.50
Dispatch	6.33
Data deps.	1.00
Overall L1	6.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles. At this rate:

21% of peak load performance is reached (20.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 41115c

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
INC %R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R14,0x260(%RAX)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
JBE 4110f0 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x5b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV (%R15),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOVSD (%RCX,%R14,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD (%R12),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0.50	0.50	7	1
JAE 411150 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x610>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV 0x13f0(%R12),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
SUB 0x13e8(%R12),%RCX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
SHR $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
IMUL $-0x55555555,%ECX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
TEST %ECX,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JLE 41124d <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x70d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV $0x10,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV -0x38(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
LEA (%RCX,%RCX,2),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0x1418(%R12),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x18(%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOVSXD (%RAX,%R14,4),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
MOV 0x1400(%R12),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV (%RCX,%RAX,8),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x38(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
LEA -0x60(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV $0x1,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 4052e0 <@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV -0x90(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x80(%RBP),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CALL 405610 <@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x1418(%R12),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV -0x88(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
JMP 411150 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x610>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1

Function	_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE
Source file and lines	NonLocalPP.hpp:126-135
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145,170
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919,1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43,63
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/unique_ptr.h:173
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Drivers/NonLocalPP.hpp:126-135

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.50 to 1.50 cycles (3.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

UCOMISD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 108 bytes (13 double precision FP elements).

General properties

nb instructions	30
nb uops	33
loop length	147
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.25	3.25	3.25	3.25	3.00	5.33	5.33	5.33	0.00	0.00	0.50	0.50	0.50	0.50
cycles	3.25	3.25	3.25	3.25	3.00	5.33	5.33	5.33	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.50
Dispatch	5.33
Data deps.	1.00
Overall L1	5.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles. At this rate:

20% of peak load performance is reached (19.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 41115c

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
INC %R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R14,0x260(%RAX)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
JBE 4110f0 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x5b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV (%R15),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOVSD (%RCX,%R14,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD (%R12),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0.50	0.50	7	1
JAE 411150 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x610>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV 0x13f0(%R12),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
SUB 0x13e8(%R12),%RCX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
SHR $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
IMUL $-0x55555555,%ECX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
TEST %ECX,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JLE 41124d <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x70d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV 0x18(%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOVSXD (%RAX,%R14,4),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
MOV 0x1400(%R12),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV (%RCX,%RAX,8),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x38(%RBP),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
LEA -0x60(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV $0x1,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 4052e0 <@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV -0x90(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x80(%RBP),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CALL 405610 <@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x1418(%R12),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV -0x88(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
JMP 411150 <_ZN11qmcplusplus10NonLocalPPIdE8evaluateERKNS_11ParticleSetERNS_12WaveFunctionE+0x610>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1

Report Configuration

Vectorization

Details

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end