OV - exec - Loop 338

0x425980 MOVUPD	(%RCX),%XMM1    [1]

0x425984 MOVUPD	0x10(%RCX),%XMM2    [1]

0x425989 MOVUPD	0x20(%RCX),%XMM3    [1]

0x42598e ADDPD	%XMM1,%XMM3

0x425992 MOVUPD	0x30(%RCX),%XMM1    [1]

0x425997 ADDPD	%XMM2,%XMM1

0x42599b ADDPD	%XMM3,%XMM1

0x42599f MOVAPD	%XMM1,%XMM2

0x4259a3 UNPCKHPD	%XMM1,%XMM2

0x4259a7 ADDSD	%XMM1,%XMM2

0x4259ab ADDSD	%XMM2,%XMM0

0x4259af ADD	$0x40,%RCX

0x4259b3 DEC	%RAX

0x4259b6 JNE	425980

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_numeric.h: 140 - 141

--------------------------------------------------------------------------------

140:       for (; __first != __last; ++__first)

141: 	__init = _GLIBCXX_MOVE_IF_20(__init) + *__first;

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_iterator.h: 1182 - 1182

--------------------------------------------------------------------------------

1182:     { return __lhs.base() != __rhs.base(); }

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.15
CQA speedup if fully vectorized	3.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks
Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE
Source	stl_numeric.h:140-141,stl_iterator.h:1182-1182
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	1.39
CQA cycles if fully vectorized	1.00
Front-end cycles	2.17
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.33
P7 cycles	0.00
P8 cycles	1.00
P9 cycles	2.50
P10 cycles	2.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	14.00
Nb uops	13.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.67
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	72.73
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	60.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	21.59
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	20.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.15
CQA speedup if fully vectorized	3.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks
Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE
Source	stl_numeric.h:140-141,stl_iterator.h:1182-1182
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	1.39
CQA cycles if fully vectorized	1.00
Front-end cycles	2.17
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.33
P7 cycles	0.00
P8 cycles	1.00
P9 cycles	2.50
P10 cycles	2.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	14.00
Nb uops	13.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.67
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	72.73
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	60.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	21.59
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	20.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE
Source file and lines	stl_numeric.h:140-141
Module	exec

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_numeric.h:140-141
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_iterator.h:1182

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 21% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Details

72% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 4 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary loop is loading 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	14
nb uops	13
loop length	56
used x86 registers	2
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.17 cycles
front end	2.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	1.33	1.33	1.33	0.00	1.00	2.50	2.50	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.50	1.33	1.33	1.33	0.00	1.00	2.50	2.50	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	2.17
Dispatch	2.50
Data deps.	3.00
Overall L1	3.00

Vectorization ratios

all	72%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	60%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

all	21%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 425980

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	FP3	Latency	Recip. throughput
MOVUPD (%RCX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.50
MOVUPD 0x10(%RCX),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.50
MOVUPD 0x20(%RCX),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.50
ADDPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
MOVUPD 0x30(%RCX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.50
ADDPD %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
ADDPD %XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
MOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKHPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	1	0.40
ADDSD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
ADDSD %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
DEC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JNE 425980 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x1a0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE
Source file and lines	stl_numeric.h:140-141
Module	exec

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_numeric.h:140-141
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_iterator.h:1182

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 21% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Details

72% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 4 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary loop is loading 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	14
nb uops	13
loop length	56
used x86 registers	2
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.17 cycles
front end	2.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	1.33	1.33	1.33	0.00	1.00	2.50	2.50	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.50	1.33	1.33	1.33	0.00	1.00	2.50	2.50	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	2.17
Dispatch	2.50
Data deps.	3.00
Overall L1	3.00

Vectorization ratios

all	72%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	60%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

all	21%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 425980

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	FP3	Latency	Recip. throughput
MOVUPD (%RCX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.50
MOVUPD 0x10(%RCX),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.50
MOVUPD 0x20(%RCX),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.50
ADDPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
MOVUPD 0x30(%RCX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.50
ADDPD %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
ADDPD %XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
MOVAPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKHPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	1	0.40
ADDSD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
ADDSD %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
DEC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JNE 425980 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x1a0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code