OV - exec - Loop 323

	Loop Id: 323	Module: exec	Source: BsplineFunctor.h:236-241	Coverage: 1.1%

0x424dd0 ADD	$0x8,%R15

0x424dd4 CMP	%R15,%RCX

0x424dd7 JE	424936

0x424ddd MOVSD	-0x38(%RBX,%R15,8),%XMM0    [6]

0x424de4 UCOMISD	%XMM0,%XMM1

0x424de8 JBE	424dfe

0x424dea MOV	%R14D,%R12D

0x424ded ADD	%R15D,%R12D

0x424df0 JE	424dfe

0x424df2 MOVSXD	%R10D,%R10

0x424df5 MOVSD	%XMM0,(%R9,%R10,8)    [4]

0x424dfb INC	%R10D

0x424dfe MOVSD	-0x30(%RBX,%R15,8),%XMM0    [6]

0x424e05 UCOMISD	%XMM0,%XMM1

0x424e09 JBE	424e21

0x424e0b LEA	(%R14,%R15,1),%R12D

0x424e0f CMP	$-0x1,%R12D

0x424e13 JE	424e21

0x424e15 MOVSXD	%R10D,%R10

0x424e18 MOVSD	%XMM0,(%R9,%R10,8)    [3]

0x424e1e INC	%R10D

0x424e21 MOVSD	-0x28(%RBX,%R15,8),%XMM0    [6]

0x424e28 UCOMISD	%XMM0,%XMM1

0x424e2c JBE	424e44

0x424e2e LEA	(%R14,%R15,1),%R12D

0x424e32 CMP	$-0x2,%R12D

0x424e36 JE	424e44

0x424e38 MOVSXD	%R10D,%R10

0x424e3b MOVSD	%XMM0,(%R9,%R10,8)    [2]

0x424e41 INC	%R10D

0x424e44 MOVSD	-0x20(%RBX,%R15,8),%XMM0    [6]

0x424e4b UCOMISD	%XMM0,%XMM1

0x424e4f JBE	424e67

0x424e51 LEA	(%R14,%R15,1),%R12D

0x424e55 CMP	$-0x3,%R12D

0x424e59 JE	424e67

0x424e5b MOVSXD	%R10D,%R10

0x424e5e MOVSD	%XMM0,(%R9,%R10,8)    [1]

0x424e64 INC	%R10D

0x424e67 MOVSD	-0x18(%RBX,%R15,8),%XMM0    [6]

0x424e6e UCOMISD	%XMM0,%XMM1

0x424e72 JBE	424e8a

0x424e74 LEA	(%R14,%R15,1),%R12D

0x424e78 CMP	$-0x4,%R12D

0x424e7c JE	424e8a

0x424e7e MOVSXD	%R10D,%R10

0x424e81 MOVSD	%XMM0,(%R9,%R10,8)    [9]

0x424e87 INC	%R10D

0x424e8a MOVSD	-0x10(%RBX,%R15,8),%XMM0    [6]

0x424e91 UCOMISD	%XMM0,%XMM1

0x424e95 JBE	424ead

0x424e97 LEA	(%R14,%R15,1),%R12D

0x424e9b CMP	$-0x5,%R12D

0x424e9f JE	424ead

0x424ea1 MOVSXD	%R10D,%R10

0x424ea4 MOVSD	%XMM0,(%R9,%R10,8)    [8]

0x424eaa INC	%R10D

0x424ead MOVSD	-0x8(%RBX,%R15,8),%XMM0    [6]

0x424eb4 UCOMISD	%XMM0,%XMM1

0x424eb8 JBE	424ed0

0x424eba LEA	(%R14,%R15,1),%R12D

0x424ebe CMP	$-0x6,%R12D

0x424ec2 JE	424ed0

0x424ec4 MOVSXD	%R10D,%R10

0x424ec7 MOVSD	%XMM0,(%R9,%R10,8)    [7]

0x424ecd INC	%R10D

0x424ed0 MOVSD	(%RBX,%R15,8),%XMM0    [6]

0x424ed6 UCOMISD	%XMM0,%XMM1

0x424eda JBE	424dd0

0x424ee0 LEA	(%R14,%R15,1),%R12D

0x424ee4 CMP	$-0x7,%R12D

0x424ee8 JE	424dd0

0x424eee MOVSXD	%R10D,%R10

0x424ef1 MOVSD	%XMM0,(%R9,%R10,8)    [5]

0x424ef7 INC	%R10D

0x424efa JMP	424dd0

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 236 - 241

--------------------------------------------------------------------------------

236:   for (int jat = 0; jat < iLimit; jat++)

237:   {

238:     real_type r = distArray[jat];

239:     // pick the distances smaller than the cutoff and avoid the reference atom

240:     if (r < cutoff_radius && iStart + jat != iat)

241:       distArrayCompressed[iCount++] = distArray[jat];

Path /

Metric	Value
CQA speedup if no scalar integer	1.28
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.04
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	micro-operation queue,
Function	_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd
Source	BsplineFunctor.h:236-241
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	13.83
CQA cycles if no scalar integer	10.83
CQA cycles if FP arith vectorized	13.83
CQA cycles if fully vectorized	1.15
Front-end cycles	13.83
DIV/SQRT cycles	10.25
P0 cycles	10.25
P1 cycles	10.25
P2 cycles	10.25
P3 cycles	9.00
P4 cycles	5.33
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	83.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.25
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.85
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.56

Metric	Value
CQA speedup if no scalar integer	1.28
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.04
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	micro-operation queue,
Function	_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd
Source	BsplineFunctor.h:236-241
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	13.83
CQA cycles if no scalar integer	10.83
CQA cycles if FP arith vectorized	13.83
CQA cycles if fully vectorized	1.15
Front-end cycles	13.83
DIV/SQRT cycles	10.25
P0 cycles	10.25
P1 cycles	10.25
P2 cycles	10.25
P3 cycles	9.00
P4 cycles	5.33
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	83.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.25
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.85
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.56

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd
Source file and lines	BsplineFunctor.h:236-241
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:236-241.

It is main loop of related source loop which is unrolled by 8 (including vectorization).
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 6561 paths individually, rerun with max-paths=6561
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 6561 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.83 to 10.83 cycles (1.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 13.83 to 1.15 cycles (12.04x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

UCOMISD: 8 occurrences

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes (8 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

General properties

nb instructions	76
nb uops	83
loop length	303
used x86 registers	7
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.83 cycles
front end	13.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.25	10.25	10.25	10.25	9.00	5.33	5.33	5.33	0.00	0.00	4.00	4.00	8.00	8.00
cycles	10.25	10.25	10.25	10.25	9.00	5.33	5.33	5.33	0.00	0.00	4.00	4.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.83
Dispatch	10.25
Overall L1	13.83

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.83 cycles. At this rate:

4% of peak load performance is reached (4.63 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.63 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.83 to 10.25 cycles (1.35x speedup).

ASM code

In the binary file, the address of the loop is: 424ddd

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
ADD $0x8,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R15,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424936 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x36>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSD -0x38(%RBX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424dfe <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x4fe>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %R14D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD %R15D,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424dfe <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x4fe>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x30(%RBX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424e21 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x521>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R14,%R15,1),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x1,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424e21 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x521>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x28(%RBX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424e44 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x544>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R14,%R15,1),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x2,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424e44 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x544>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x20(%RBX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424e67 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x567>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R14,%R15,1),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x3,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424e67 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x567>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x18(%RBX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424e8a <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x58a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R14,%R15,1),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x4,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424e8a <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x58a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x10(%RBX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424ead <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x5ad>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R14,%R15,1),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x5,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424ead <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x5ad>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x8(%RBX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424ed0 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x5d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R14,%R15,1),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x6,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424ed0 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x5d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD (%RBX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424dd0 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x4d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R14,%R15,1),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x7,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424dd0 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x4d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JMP 424dd0 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x4d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1

Function	_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd
Source file and lines	BsplineFunctor.h:236-241
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 6561 paths individually, rerun with max-paths=6561
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

UCOMISD: 8 occurrences

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

General properties

nb instructions	76
nb uops	83
loop length	303
used x86 registers	7
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.83 cycles
front end	13.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.25	10.25	10.25	10.25	9.00	5.33	5.33	5.33	0.00	0.00	4.00	4.00	8.00	8.00
cycles	10.25	10.25	10.25	10.25	9.00	5.33	5.33	5.33	0.00	0.00	4.00	4.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.83
Dispatch	10.25
Overall L1	13.83

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.83 cycles. At this rate:

4% of peak load performance is reached (4.63 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.63 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 424ddd

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
ADD $0x8,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R15,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424936 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x36>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSD -0x38(%RBX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424dfe <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x4fe>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %R14D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD %R15D,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424dfe <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x4fe>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x30(%RBX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424e21 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x521>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R14,%R15,1),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x1,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424e21 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x521>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x28(%RBX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424e44 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x544>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R14,%R15,1),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x2,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424e44 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x544>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x20(%RBX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424e67 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x567>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R14,%R15,1),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x3,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424e67 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x567>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x18(%RBX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424e8a <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x58a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R14,%R15,1),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x4,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424e8a <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x58a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x10(%RBX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424ead <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x5ad>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R14,%R15,1),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x5,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424ead <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x5ad>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x8(%RBX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424ed0 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x5d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R14,%R15,1),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x6,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424ed0 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x5d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD (%RBX,%R15,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424dd0 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x4d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R14,%R15,1),%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x7,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424dd0 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x4d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,(%R9,%R10,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JMP 424dd0 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x4d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code