OV - exec - Loop 321

	Loop Id: 321	Module: exec	Source: BsplineFunctor.h:246-260 [...]	Coverage: 0.04%

0x424b60 MOVAPD	(%R9,%RDX,8),%XMM2    [4]

0x424b66 MULPD	-0x1e0(%RBP),%XMM2    [8]

0x424b6e CVTTPD2DQ	%XMM2,%XMM4

0x424b72 CVTDQ2PD	%XMM4,%XMM1

0x424b76 SUBPD	%XMM1,%XMM2

0x424b7a MOVAPD	%XMM2,%XMM8

0x424b7f MULPD	%XMM2,%XMM8

0x424b84 MOVAPD	%XMM8,%XMM11

0x424b89 MOVAPD	-0x1c0(%RBP),%XMM12    [8]

0x424b92 MULPD	%XMM8,%XMM12

0x424b97 MOVAPD	-0x1b0(%RBP),%XMM1    [8]

0x424b9f MULPD	%XMM2,%XMM1

0x424ba3 PXOR	%XMM13,%XMM13

0x424ba8 MULPD	%XMM2,%XMM11

0x424bad PCMPGTD	%XMM4,%XMM13

0x424bb2 PUNPCKLDQ	%XMM13,%XMM4

0x424bb7 PSLLQ	$0x3,%XMM4

0x424bbc ADDPD	%XMM12,%XMM1

0x424bc1 PADDQ	-0x190(%RBP),%XMM4    [8]

0x424bc9 MOVQ	%XMM4,%RSI

0x424bce PSHUFD	$-0x12,%XMM4,%XMM12

0x424bd4 MOVAPD	%XMM11,%XMM13

0x424bd9 MOVQ	%XMM12,%RDI

0x424bde MOVAPD	-0x170(%RBP),%XMM12    [8]

0x424be7 MULPD	%XMM8,%XMM12

0x424bec MULPD	-0x1d0(%RBP),%XMM13    [8]

0x424bf5 MOVAPD	-0x160(%RBP),%XMM5    [8]

0x424bfd MULPD	%XMM2,%XMM5

0x424c01 ADDPD	%XMM12,%XMM5

0x424c06 ADDPD	-0x1a0(%RBP),%XMM1    [8]

0x424c0e MOVAPD	-0x180(%RBP),%XMM12    [8]

0x424c17 MULPD	%XMM11,%XMM12

0x424c1c ADDPD	-0x150(%RBP),%XMM5    [8]

0x424c24 ADDPD	%XMM13,%XMM1

0x424c29 ADDPD	%XMM12,%XMM5

0x424c2e MOVDQA	%XMM4,%XMM13

0x424c33 PADDQ	0xf2b34(%RIP),%XMM13    [7]

0x424c3c MOVSD	(%RSI),%XMM12    [3]

0x424c41 MOVQ	%XMM13,%RSI

0x424c46 PSHUFD	$-0x12,%XMM13,%XMM13

0x424c4c MOVHPD	(%RDI),%XMM12    [1]

0x424c51 MOVQ	%XMM13,%RDI

0x424c56 MOVSD	(%RSI),%XMM13    [2]

0x424c5b MOVHPD	(%RDI),%XMM13    [6]

0x424c60 MULPD	%XMM5,%XMM13

0x424c65 MOVAPD	%XMM6,%XMM5

0x424c69 MULPD	%XMM8,%XMM5

0x424c6e MULPD	%XMM1,%XMM12

0x424c73 MOVAPD	%XMM7,%XMM1

0x424c77 MULPD	%XMM2,%XMM1

0x424c7b ADDPD	%XMM5,%XMM1

0x424c7f MOVAPD	-0x140(%RBP),%XMM5    [8]

0x424c87 MULPD	%XMM11,%XMM5

0x424c8c ADDPD	%XMM9,%XMM1

0x424c91 ADDPD	%XMM5,%XMM1

0x424c95 ADDPD	%XMM0,%XMM12

0x424c9a MOVDQA	%XMM4,%XMM0

0x424c9e PADDQ	0xf2ada(%RIP),%XMM0    [7]

0x424ca6 MOVQ	%XMM0,%RSI

0x424cab PSHUFD	$-0x12,%XMM0,%XMM0

0x424cb0 MOVQ	%XMM0,%RDI

0x424cb5 MOVSD	(%RSI),%XMM5    [9]

0x424cb9 MOVHPD	(%RDI),%XMM5    [11]

0x424cbd MULPD	%XMM1,%XMM5

0x424cc1 ADDPD	%XMM13,%XMM5

0x424cc6 ADDPD	%XMM12,%XMM5

0x424ccb MULPD	%XMM14,%XMM8

0x424cd0 MULPD	%XMM10,%XMM2

0x424cd5 ADDPD	%XMM8,%XMM2

0x424cda MULPD	%XMM15,%XMM11

0x424cdf ADDPD	%XMM3,%XMM2

0x424ce3 ADDPD	%XMM11,%XMM2

0x424ce8 PADDQ	0xf2aa0(%RIP),%XMM4    [7]

0x424cf0 MOVQ	%XMM4,%RSI

0x424cf5 PSHUFD	$-0x12,%XMM4,%XMM0

0x424cfa MOVQ	%XMM0,%RDI

0x424cff MOVSD	(%RSI),%XMM0    [5]

0x424d03 MOVHPD	(%RDI),%XMM0    [10]

0x424d07 MULPD	%XMM2,%XMM0

0x424d0b ADDPD	%XMM5,%XMM0

0x424d0f ADD	$0x2,%RDX

0x424d13 CMP	%RCX,%RDX

0x424d16 JB	424b60

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1064 - 1064

--------------------------------------------------------------------------------

1064: 	return *(this->_M_impl._M_start + __n);

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 246 - 260

--------------------------------------------------------------------------------

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.53
CQA speedup if fully vectorized	2.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd
Source	stl_vector.h:1064-1064,BsplineFunctor.h:246-260
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	13.67
CQA cycles if no scalar integer	13.67
CQA cycles if FP arith vectorized	8.92
CQA cycles if fully vectorized	5.52
Front-end cycles	13.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	7.67
P5 cycles	7.67
P6 cycles	7.67
P7 cycles	13.25
P8 cycles	13.33
P9 cycles	13.25
P10 cycles	13.17
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	9
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	83.00
Nb uops	82.00
Nb loads	23.00
Nb stores	0.00
Nb stack references	11.00
FLOP/cycle	5.27
Nb FLOP add-sub	34.00
Nb FLOP mul	38.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.24
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	80.00
Vectorization ratio load	65.22
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	68.00
Vector-efficiency ratio all	22.19
Vector-efficiency ratio load	20.65
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.53
CQA speedup if fully vectorized	2.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd
Source	stl_vector.h:1064-1064,BsplineFunctor.h:246-260
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	2
CQA cycles	13.67
CQA cycles if no scalar integer	13.67
CQA cycles if FP arith vectorized	8.92
CQA cycles if fully vectorized	5.52
Front-end cycles	13.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	7.67
P5 cycles	7.67
P6 cycles	7.67
P7 cycles	13.25
P8 cycles	13.33
P9 cycles	13.25
P10 cycles	13.17
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	9
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	83.00
Nb uops	82.00
Nb loads	23.00
Nb stores	0.00
Nb stack references	11.00
FLOP/cycle	5.27
Nb FLOP add-sub	34.00
Nb FLOP mul	38.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.24
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	80.00
Vectorization ratio load	65.22
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	68.00
Vector-efficiency ratio all	22.19
Vector-efficiency ratio load	20.65
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd
Source file and lines	BsplineFunctor.h:246-260
Module	exec

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:246-260

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 22% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 13.67 to 5.52 cycles (2.48x speedup).

Details

80% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

65% of SSE/AVX loads are used in vector version.
68% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 4 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CVTDQ2PD (INT32 to FP64, SIMD): 1 occurrences
CVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

36 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 72 FP arithmetical operations:

34: addition or subtraction
38: multiply

The binary loop is loading 304 bytes (38 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.24 FP operations per loaded or stored byte.

General properties

nb instructions	83
nb uops	82
loop length	444
used x86 registers	6
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	11
ADD-SUB / MUL ratio	0.89

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.67 cycles
front end	13.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	7.67	7.67	7.67	13.25	13.33	13.25	13.17	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	7.67	7.67	7.67	13.25	13.33	13.25	13.17	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	9.00

Cycles summary

Front-end	13.67
Dispatch	13.33
Data deps.	9.00
Overall L1	13.67

Vectorization ratios

INT

all	65%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	57%

all	85%
load	57%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	80%
load	65%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	68%

Vector efficiency ratios

INT

all	19%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	23%
load	19%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	22%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.67 cycles. At this rate:

23% of peak load performance is reached (22.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 424b60

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOVAPD (%R9,%RDX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD -0x1e0(%RBP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
CVTTPD2DQ %XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
CVTDQ2PD %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
SUBPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM2,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM2,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM8,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVAPD -0x1c0(%RBP),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM8,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD -0x1b0(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
PXOR %XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
MULPD %XMM2,%XMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
PCMPGTD %XMM4,%XMM13	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
PUNPCKLDQ %XMM13,%XMM4	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
PSLLQ $0x3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
ADDPD %XMM12,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
PADDQ -0x190(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
MOVQ %XMM4,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
PSHUFD $-0x12,%XMM4,%XMM12	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVAPD %XMM11,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVQ %XMM12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOVAPD -0x170(%RBP),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM8,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD -0x1d0(%RBP),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVAPD -0x160(%RBP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM2,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM12,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD -0x1a0(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVAPD -0x180(%RBP),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD -0x150(%RBP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM13,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM12,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVDQA %XMM4,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PADDQ 0xf2b34(%RIP),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
MOVSD (%RSI),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVQ %XMM13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
PSHUFD $-0x12,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVHPD (%RDI),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
MOVQ %XMM13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOVSD (%RSI),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVHPD (%RDI),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
MULPD %XMM5,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM6,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM8,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM1,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM7,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM5,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD -0x140(%RBP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM11,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM9,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM5,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM0,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVDQA %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PADDQ 0xf2ada(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
MOVQ %XMM0,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
PSHUFD $-0x12,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVQ %XMM0,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOVSD (%RSI),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVHPD (%RDI),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
MULPD %XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM13,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM12,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPD %XMM14,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM10,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM8,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPD %XMM15,%XMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM11,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
PADDQ 0xf2aa0(%RIP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
MOVQ %XMM4,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
PSHUFD $-0x12,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVQ %XMM0,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOVSD (%RSI),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVHPD (%RDI),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
MULPD %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADD $0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JB 424b60 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x260>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd
Source file and lines	BsplineFunctor.h:246-260
Module	exec

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:246-260

It is main loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

80% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

65% of SSE/AVX loads are used in vector version.
68% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 4 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CVTDQ2PD (INT32 to FP64, SIMD): 1 occurrences
CVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

36 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 72 FP arithmetical operations:

34: addition or subtraction
38: multiply

The binary loop is loading 304 bytes (38 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.24 FP operations per loaded or stored byte.

General properties

nb instructions	83
nb uops	82
loop length	444
used x86 registers	6
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	11
ADD-SUB / MUL ratio	0.89

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.67 cycles
front end	13.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	7.67	7.67	7.67	13.25	13.33	13.25	13.17	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	7.67	7.67	7.67	13.25	13.33	13.25	13.17	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	9.00

Cycles summary

Front-end	13.67
Dispatch	13.33
Data deps.	9.00
Overall L1	13.67

Vectorization ratios

INT

all	65%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	57%

all	85%
load	57%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	80%
load	65%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	68%

Vector efficiency ratios

INT

all	19%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	23%
load	19%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	22%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.67 cycles. At this rate:

23% of peak load performance is reached (22.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 424b60

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOVAPD (%R9,%RDX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD -0x1e0(%RBP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
CVTTPD2DQ %XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
CVTDQ2PD %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
SUBPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM2,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM2,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM8,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVAPD -0x1c0(%RBP),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM8,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD -0x1b0(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
PXOR %XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
MULPD %XMM2,%XMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
PCMPGTD %XMM4,%XMM13	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
PUNPCKLDQ %XMM13,%XMM4	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
PSLLQ $0x3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
ADDPD %XMM12,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
PADDQ -0x190(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
MOVQ %XMM4,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
PSHUFD $-0x12,%XMM4,%XMM12	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVAPD %XMM11,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVQ %XMM12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOVAPD -0x170(%RBP),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM8,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD -0x1d0(%RBP),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVAPD -0x160(%RBP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM2,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM12,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD -0x1a0(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVAPD -0x180(%RBP),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD -0x150(%RBP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM13,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM12,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVDQA %XMM4,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PADDQ 0xf2b34(%RIP),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
MOVSD (%RSI),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVQ %XMM13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
PSHUFD $-0x12,%XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVHPD (%RDI),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
MOVQ %XMM13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOVSD (%RSI),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVHPD (%RDI),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
MULPD %XMM5,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM6,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM8,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM1,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM7,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM5,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD -0x140(%RBP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM11,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM9,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM5,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM0,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVDQA %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PADDQ 0xf2ada(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
MOVQ %XMM0,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
PSHUFD $-0x12,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVQ %XMM0,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOVSD (%RSI),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVHPD (%RDI),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
MULPD %XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM13,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM12,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPD %XMM14,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM10,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM8,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPD %XMM15,%XMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM11,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
PADDQ 0xf2aa0(%RIP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
MOVQ %XMM4,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
PSHUFD $-0x12,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVQ %XMM0,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOVSD (%RSI),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVHPD (%RDI),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
MULPD %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDPD %XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADD $0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JB 424b60 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x260>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code