OV - exec - Loop 319

	Loop Id: 319	Module: exec	Source: BsplineFunctor.h:291-298	Coverage: 0.16%

0x424200 ADD	$0x4,%R13

0x424204 CMP	%R13,%RCX

0x424207 JE	423840

0x42420d MOVSD	-0x18(%R15,%R13,8),%XMM1    [7]

0x424214 UCOMISD	%XMM1,%XMM0

0x424218 JBE	424231

0x42421a MOV	%R12D,%R11D

0x42421d ADD	%R13D,%R11D

0x424220 JE	424231

0x424222 MOVSXD	%EBX,%RBX

0x424225 MOV	%R13D,(%RAX,%RBX,4)    [2]

0x424229 MOVSD	%XMM1,(%R10,%RBX,8)    [6]

0x42422f INC	%EBX

0x424231 MOVSD	-0x10(%R15,%R13,8),%XMM1    [7]

0x424238 UCOMISD	%XMM1,%XMM0

0x42423c JBE	42425b

0x42423e LEA	(%R12,%R13,1),%R11D

0x424242 CMP	$-0x1,%R11D

0x424246 JE	42425b

0x424248 MOVSXD	%EBX,%RBX

0x42424b LEA	0x1(%R13),%R11D

0x42424f MOV	%R11D,(%RAX,%RBX,4)    [1]

0x424253 MOVSD	%XMM1,(%R10,%RBX,8)    [5]

0x424259 INC	%EBX

0x42425b MOVSD	-0x8(%R15,%R13,8),%XMM1    [7]

0x424262 UCOMISD	%XMM1,%XMM0

0x424266 JBE	424285

0x424268 LEA	(%R12,%R13,1),%R11D

0x42426c CMP	$-0x2,%R11D

0x424270 JE	424285

0x424272 MOVSXD	%EBX,%RBX

0x424275 LEA	0x2(%R13),%R11D

0x424279 MOV	%R11D,(%RAX,%RBX,4)    [9]

0x42427d MOVSD	%XMM1,(%R10,%RBX,8)    [4]

0x424283 INC	%EBX

0x424285 MOVSD	(%R15,%R13,8),%XMM1    [7]

0x42428b UCOMISD	%XMM1,%XMM0

0x42428f JBE	424200

0x424295 LEA	(%R12,%R13,1),%R11D

0x424299 CMP	$-0x3,%R11D

0x42429d JE	424200

0x4242a3 MOVSXD	%EBX,%RBX

0x4242a6 LEA	0x3(%R13),%R11D

0x4242aa MOV	%R11D,(%RAX,%RBX,4)    [8]

0x4242ae MOVSD	%XMM1,(%R10,%RBX,8)    [3]

0x4242b4 INC	%EBX

0x4242b6 JMP	424200

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 291 - 298

--------------------------------------------------------------------------------

291:   for (int jat = 0; jat < iLimit; jat++)

292:   {

293:     real_type r = distArray[jat];

294:     if (r < cutoff_radius && iStart + jat != iat)

295:     {

296:       distIndices[iCount]         = jat;

297:       distArrayCompressed[iCount] = r;

298:       iCount++;

Path /

Metric	Value
CQA speedup if no scalar integer	1.52
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.53
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	micro-operation queue,
Function	_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi
Source	BsplineFunctor.h:291-298
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	8.33
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	8.33
CQA cycles if fully vectorized	0.66
Front-end cycles	8.33
DIV/SQRT cycles	6.00
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	6.00
P3 cycles	5.00
P4 cycles	4.00
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	50.00
Nb loads	4.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.60
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	48.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.94
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.72

Metric	Value
CQA speedup if no scalar integer	1.52
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.53
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	micro-operation queue,
Function	_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi
Source	BsplineFunctor.h:291-298
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	8.33
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	8.33
CQA cycles if fully vectorized	0.66
Front-end cycles	8.33
DIV/SQRT cycles	6.00
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	6.00
P3 cycles	5.00
P4 cycles	4.00
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	50.00
Nb loads	4.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.60
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	48.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.94
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.72

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi
Source file and lines	BsplineFunctor.h:291-298
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:291-298.

It is main loop of related source loop which is unrolled by 4 (including vectorization).
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 81 paths individually, rerun with max-paths=81
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 81 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.33 to 5.50 cycles (1.52x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.33 to 0.66 cycles (12.53x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

UCOMISD: 4 occurrences

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes (4 double precision FP elements). The binary loop is storing 48 bytes (6 double precision FP elements).

General properties

nb instructions	47
nb uops	50
loop length	187
used x86 registers	8
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.33 cycles
front end	8.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.00	6.00	6.00	6.00	5.00	4.00	4.00	4.00	0.00	0.00	2.00	2.00	4.00	4.00
cycles	6.00	6.00	6.00	6.00	5.00	4.00	4.00	4.00	0.00	0.00	2.00	2.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.33
Dispatch	6.00
Overall L1	8.33

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.33 cycles. At this rate:

4% of peak load performance is reached (3.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (5.76 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.33 to 6.00 cycles (1.39x speedup).

ASM code

In the binary file, the address of the loop is: 42420d

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
ADD $0x4,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R13,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 423840 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x40>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSD -0x18(%R15,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM1,%XMM0	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424231 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa31>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %R12D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD %R13D,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424231 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa31>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %EBX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R13D,(%RAX,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOVSD %XMM1,(%R10,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x10(%R15,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM1,%XMM0	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 42425b <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa5b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R12,%R13,1),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x1,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 42425b <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa5b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %EBX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%R13),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R11D,(%RAX,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOVSD %XMM1,(%R10,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x8(%R15,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM1,%XMM0	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424285 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa85>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R12,%R13,1),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x2,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424285 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa85>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %EBX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA 0x2(%R13),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R11D,(%RAX,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOVSD %XMM1,(%R10,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD (%R15,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM1,%XMM0	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424200 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa00>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R12,%R13,1),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x3,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424200 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa00>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %EBX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA 0x3(%R13),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R11D,(%RAX,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOVSD %XMM1,(%R10,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JMP 424200 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa00>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1

Function	_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi
Source file and lines	BsplineFunctor.h:291-298
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 81 paths individually, rerun with max-paths=81
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.33 to 5.50 cycles (1.52x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

UCOMISD: 4 occurrences

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

General properties

nb instructions	47
nb uops	50
loop length	187
used x86 registers	8
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.33 cycles
front end	8.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.00	6.00	6.00	6.00	5.00	4.00	4.00	4.00	0.00	0.00	2.00	2.00	4.00	4.00
cycles	6.00	6.00	6.00	6.00	5.00	4.00	4.00	4.00	0.00	0.00	2.00	2.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.33
Dispatch	6.00
Overall L1	8.33

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.33 cycles. At this rate:

4% of peak load performance is reached (3.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (5.76 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 42420d

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
ADD $0x4,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R13,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 423840 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x40>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSD -0x18(%R15,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM1,%XMM0	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424231 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa31>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV %R12D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD %R13D,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424231 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa31>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %EBX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R13D,(%RAX,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOVSD %XMM1,(%R10,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x10(%R15,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM1,%XMM0	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 42425b <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa5b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R12,%R13,1),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x1,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 42425b <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa5b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %EBX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%R13),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R11D,(%RAX,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOVSD %XMM1,(%R10,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x8(%R15,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM1,%XMM0	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424285 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa85>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R12,%R13,1),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x2,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424285 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa85>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %EBX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA 0x2(%R13),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R11D,(%RAX,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOVSD %XMM1,(%R10,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSD (%R15,%R13,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
UCOMISD %XMM1,%XMM0	2	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 424200 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa00>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
LEA (%R12,%R13,1),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x3,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 424200 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa00>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %EBX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA 0x3(%R13),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R11D,(%RAX,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOVSD %XMM1,(%R10,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %EBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JMP 424200 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0xa00>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code