OV - exec - Function _ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system

	Function: _ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv	Module: exec	Source: NewTimer.cpp:85-120 [...]	Coverage: 0.03%

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/chrono: 227 - 666

--------------------------------------------------------------------------------

227: 	      static_cast<_CR>(__d.count()) / static_cast<_CR>(_CF::den)));

[...]

666: 	return __cd(__cd(__lhs).count() - __cd(__rhs).count());

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp: 85 - 120

--------------------------------------------------------------------------------

85: {

86:   if (active)

[...]

99:     for (int level = omp_get_level(); level > 0; level--)

100:       if (omp_get_ancestor_thread_num(level) != 0)

101:         is_true_master = false;

102:     if (is_true_master)

103:     {

104:       std::chrono::duration<double> elapsed = CLOCK::now() - start_time;

105:       total_time += elapsed.count();

106:       num_calls++;

107:

108:       per_stack_total_time[current_stack_key] += elapsed.count();

109:       per_stack_num_calls[current_stack_key] += 1;

110:

111:       if (manager)

112:         manager->pop_timer(this);

[...]

120: }

0x497fd0 PUSH	%RBP

0x497fd1 MOV	%RSP,%RBP

0x497fd4 PUSH	%R15

0x497fd6 PUSH	%R14

0x497fd8 PUSH	%R13

0x497fda PUSH	%R12

0x497fdc PUSH	%RBX

0x497fdd SUB	$0x18,%RSP

0x497fe1 CMPB	$0,0x38(%RDI)

0x497fe5 JE	49815b

0x497feb MOV	%RDI,%RBX

0x497fee CALL	405990 <omp_get_level@plt>

0x497ff3 TEST	%EAX,%EAX

0x497ff5 JLE	4980e1

0x497ffb MOV	%RBX,-0x40(%RBP)

0x497fff MOV	$0x1,%R14B

0x498002 MOV	%EAX,-0x2c(%RBP)

0x498005 CMP	$0x8,%EAX

0x498008 JB	4980ad

0x49800e MOV	-0x2c(%RBP),%EAX

0x498011 MOV	%EAX,%ECX

0x498013 SHR	$0x3,%ECX

0x498016 MOV	$0x1,%R14B

0x498019 MOV	%EAX,%R15D

0x49801c NOPL	(%RAX)

(1570) 0x498020 MOV	%ECX,-0x38(%RBP)

(1570) 0x498023 MOV	%R15D,%EDI

(1570) 0x498026 CALL	405370 <omp_get_ancestor_thread_num@plt>

(1570) 0x49802b MOV	%EAX,%R12D

(1570) 0x49802e LEA	-0x1(%R15),%EDI

(1570) 0x498032 CALL	405370 <omp_get_ancestor_thread_num@plt>

(1570) 0x498037 MOV	%EAX,%R13D

(1570) 0x49803a OR	%R12D,%R13D

(1570) 0x49803d LEA	-0x2(%R15),%EDI

(1570) 0x498041 CALL	405370 <omp_get_ancestor_thread_num@plt>

(1570) 0x498046 MOV	%EAX,%R12D

(1570) 0x498049 LEA	-0x3(%R15),%EDI

(1570) 0x49804d CALL	405370 <omp_get_ancestor_thread_num@plt>

(1570) 0x498052 MOV	%EAX,%EBX

(1570) 0x498054 OR	%R12D,%EBX

(1570) 0x498057 OR	%R13D,%EBX

(1570) 0x49805a LEA	-0x4(%R15),%EDI

(1570) 0x49805e CALL	405370 <omp_get_ancestor_thread_num@plt>

(1570) 0x498063 MOV	%EAX,%R12D

(1570) 0x498066 LEA	-0x5(%R15),%EDI

(1570) 0x49806a CALL	405370 <omp_get_ancestor_thread_num@plt>

(1570) 0x49806f MOV	%EAX,%R13D

(1570) 0x498072 OR	%R12D,%R13D

(1570) 0x498075 OR	%EBX,%R13D

(1570) 0x498078 LEA	-0x6(%R15),%EDI

(1570) 0x49807c CALL	405370 <omp_get_ancestor_thread_num@plt>

(1570) 0x498081 MOV	%EAX,%EBX

(1570) 0x498083 LEA	-0x7(%R15),%EDI

(1570) 0x498087 CALL	405370 <omp_get_ancestor_thread_num@plt>

(1570) 0x49808c MOV	-0x38(%RBP),%ECX

(1570) 0x49808f OR	%EBX,%EAX

(1570) 0x498091 MOVZX	%R14B,%R14D

(1570) 0x498095 OR	%R13D,%EAX

(1570) 0x498098 MOV	$0,%EAX

(1570) 0x49809d CMOVNE	%EAX,%R14D

(1570) 0x4980a1 ADD	$-0x8,%R15D

(1570) 0x4980a5 DEC	%ECX

(1570) 0x4980a7 JNE	498020

0x4980ad MOV	-0x2c(%RBP),%R15D

0x4980b1 MOV	%R15D,%EAX

0x4980b4 AND	$-0x8,%EAX

0x4980b7 SUB	%EAX,%R15D

0x4980ba JBE	4980d7

0x4980bc XOR	%EBX,%EBX

0x4980be XCHG	%AX,%AX

(1569) 0x4980c0 MOV	%R15D,%EDI

(1569) 0x4980c3 CALL	405370 <omp_get_ancestor_thread_num@plt>

(1569) 0x4980c8 TEST	%EAX,%EAX

(1569) 0x4980ca MOVZX	%R14B,%R14D

(1569) 0x4980ce CMOVNE	%EBX,%R14D

(1569) 0x4980d2 DEC	%R15D

(1569) 0x4980d5 JNE	4980c0

0x4980d7 TEST	$0x1,%R14B

0x4980db MOV	-0x40(%RBP),%RBX

0x4980df JE	49815b

0x4980e1 CALL	405a80 <_ZNSt6chrono3_V212system_clock3nowEv@plt>

0x4980e6 SUB	(%RBX),%RAX

0x4980e9 CVTSI2SD	%RAX,%XMM1

0x4980ee MULSD	0x7f5c2(%RIP),%XMM1

0x4980f6 MOVSD	%XMM1,-0x38(%RBP)

0x4980fb MOVSD	0x8(%RBX),%XMM0

0x498100 ADDSD	%XMM1,%XMM0

0x498104 MOVSD	%XMM0,0x8(%RBX)

0x498109 INCQ	0x10(%RBX)

0x49810d LEA	0x68(%RBX),%RDI

0x498111 LEA	0x50(%RBX),%R14

0x498115 MOV	%R14,%RSI

0x498118 CALL	498170 <_ZNSt3mapIN11qmcplusplus13StackKeyParamILi2EEEdSt4lessIS2_ESaISt4pairIKS2_dEEEixERS6_>

0x49811d MOVSD	-0x38(%RBP),%XMM0

0x498122 ADDSD	(%RAX),%XMM0

0x498126 MOVSD	%XMM0,(%RAX)

0x49812a LEA	0x98(%RBX),%RDI

0x498131 MOV	%R14,%RSI

0x498134 CALL	4982f0 <_ZNSt3mapIN11qmcplusplus13StackKeyParamILi2EEElSt4lessIS2_ESaISt4pairIKS2_lEEEixERS6_>

0x498139 INCQ	(%RAX)

0x49813c MOV	0x48(%RBX),%RDI

0x498140 TEST	%RDI,%RDI

0x498143 JE	49815b

0x498145 MOV	%RBX,%RSI

0x498148 ADD	$0x18,%RSP

0x49814c POP	%RBX

0x49814d POP	%R12

0x49814f POP	%R13

0x498151 POP	%R14

0x498153 POP	%R15

0x498155 POP	%RBP

0x498156 JMP	49dec0

0x49815b ADD	$0x18,%RSP

0x49815f POP	%RBX

0x498160 POP	%R12

0x498162 POP	%R13

0x498164 POP	%R14

0x498166 POP	%R15

0x498168 POP	%RBP

0x498169 RET

0x49816a NOPW	(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	NewTimer.cpp:85-120
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/chrono:227,666
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:85-86,99-112,120

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.33 to 3.17 cycles (4.21x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 13.33 to 0.97 cycles (13.76x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_ZNSt3mapIN11qmcplusplus13StackKeyParamILi2EEEdSt4lessIS2_ESaISt4pairIKS2_dEEEixERS6_: 1 occurrences
_ZNSt3mapIN11qmcplusplus13StackKeyParamILi2EEElSt4lessIS2_ESaISt4pairIKS2_lEEEixERS6_: 1 occurrences
_ZNSt6chrono3_V212system_clock3nowEv@plt: 1 occurrences
omp_get_level@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CVTSI2SD: 1 occurrences
INC: 2 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:

use march=native

Conversion instructions

Detected expensive conversion instructions.

Details

CVTSI2SD (INT32/64 to FP64, scalar): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

2: addition or subtraction
1: multiply

The binary function is loading 81 bytes (10 double precision FP elements). The binary function is storing 52 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	76
nb uops	80
loop length	252
used x86 registers	11
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.33 cycles
front end	13.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.50	6.50	6.50	6.50	6.00	7.00	7.00	7.00	0.50	0.50	1.50	1.50	1.50	1.50
cycles	6.50	6.50	6.50	6.50	6.00	7.00	7.00	7.00	0.50	0.50	1.50	1.50	1.50	1.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.33
Dispatch	7.00
Overall L1	13.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	8%
load	8%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	10%
store	11%
mul	12%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.33 cycles. At this rate:

6% of peak load performance is reached (6.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.90 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.33 to 7.00 cycles (1.90x speedup).

ASM code

In the binary file, the address of the function is: 497fd0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMPB $0,0x38(%RDI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JE 49815b <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x18b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 405990 <omp_get_level@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 4980e1 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x111>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RBX,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV $0x1,%R14B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
CMP $0x8,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JB 4980ad <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0xdd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%ECX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV $0x1,%R14B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EAX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV -0x2c(%RBP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x8,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SUB %EAX,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JBE 4980d7 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x107>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
TEST $0x1,%R14B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x40(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JE 49815b <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x18b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CALL 405a80 <_ZNSt6chrono3_V212system_clock3nowEv@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
SUB (%RBX),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
CVTSI2SD %RAX,%XMM1	2	0	0	1	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1.42
MULSD 0x7f5c2(%RIP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVSD %XMM1,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD 0x8(%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVSD %XMM0,0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
INCQ 0x10(%RBX)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x68(%RBX),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x50(%RBX),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 498170 <_ZNSt3mapIN11qmcplusplus13StackKeyParamILi2EEEdSt4lessIS2_ESaISt4pairIKS2_dEEEixERS6_>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVSD -0x38(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADDSD (%RAX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVSD %XMM0,(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
LEA 0x98(%RBX),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 4982f0 <_ZNSt3mapIN11qmcplusplus13StackKeyParamILi2EEElSt4lessIS2_ESaISt4pairIKS2_lEEEixERS6_>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
INCQ (%RAX)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x48(%RBX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
TEST %RDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 49815b <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x18b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
JMP 49dec0 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINSt6chrono3_V212system_clockEEEE9pop_timerEPS5_>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	NewTimer.cpp:85-120
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/chrono:227,666
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:85-86,99-112,120

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.33 to 3.17 cycles (4.21x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

_ZNSt3mapIN11qmcplusplus13StackKeyParamILi2EEEdSt4lessIS2_ESaISt4pairIKS2_dEEEixERS6_: 1 occurrences
_ZNSt3mapIN11qmcplusplus13StackKeyParamILi2EEElSt4lessIS2_ESaISt4pairIKS2_lEEEixERS6_: 1 occurrences
_ZNSt6chrono3_V212system_clock3nowEv@plt: 1 occurrences
omp_get_level@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CVTSI2SD: 1 occurrences
INC: 2 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:

use march=native

Conversion instructions

Detected expensive conversion instructions.

Details

CVTSI2SD (INT32/64 to FP64, scalar): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

2: addition or subtraction
1: multiply

The binary function is loading 81 bytes (10 double precision FP elements). The binary function is storing 52 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	76
nb uops	80
loop length	252
used x86 registers	11
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.33 cycles
front end	13.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.50	6.50	6.50	6.50	6.00	7.00	7.00	7.00	0.50	0.50	1.50	1.50	1.50	1.50
cycles	6.50	6.50	6.50	6.50	6.00	7.00	7.00	7.00	0.50	0.50	1.50	1.50	1.50	1.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.33
Dispatch	7.00
Overall L1	13.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	8%
load	8%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	10%
store	11%
mul	12%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.33 cycles. At this rate:

6% of peak load performance is reached (6.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.90 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 497fd0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMPB $0,0x38(%RDI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JE 49815b <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x18b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 405990 <omp_get_level@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 4980e1 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x111>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RBX,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV $0x1,%R14B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
CMP $0x8,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JB 4980ad <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0xdd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%ECX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV $0x1,%R14B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EAX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV -0x2c(%RBP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x8,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SUB %EAX,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JBE 4980d7 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x107>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
TEST $0x1,%R14B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x40(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JE 49815b <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x18b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CALL 405a80 <_ZNSt6chrono3_V212system_clock3nowEv@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
SUB (%RBX),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
CVTSI2SD %RAX,%XMM1	2	0	0	1	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1.42
MULSD 0x7f5c2(%RIP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVSD %XMM1,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD 0x8(%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVSD %XMM0,0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
INCQ 0x10(%RBX)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x68(%RBX),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x50(%RBX),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 498170 <_ZNSt3mapIN11qmcplusplus13StackKeyParamILi2EEEdSt4lessIS2_ESaISt4pairIKS2_dEEEixERS6_>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVSD -0x38(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADDSD (%RAX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVSD %XMM0,(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
LEA 0x98(%RBX),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 4982f0 <_ZNSt3mapIN11qmcplusplus13StackKeyParamILi2EEElSt4lessIS2_ESaISt4pairIKS2_lEEEixERS6_>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
INCQ (%RAX)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x48(%RBX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
TEST %RDI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 49815b <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x18b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
JMP 49dec0 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINSt6chrono3_V212system_clockEEEE9pop_timerEPS5_>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Name	Coverage (%)	Time (s)
▼_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv–	0.03	0.07
○Loop 1569 - NewTimer.cpp:99-100 - exec	0	0
○Loop 1570 - NewTimer.cpp:86-100 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code